From 56550cce3389357bf0bb2c1fdc7d9a6edbc319ab Mon Sep 17 00:00:00 2001 From: Davit Grigoryan Date: Mon, 30 Mar 2026 10:25:54 +0000 Subject: initial its impl --- src/gpgpu-sim/gpu-sim.cc | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) (limited to 'src/gpgpu-sim/gpu-sim.cc') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 9055502..1f7de38 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -327,7 +327,26 @@ void memory_config::reg_options(class OptionParser *opp) { void shader_core_config::reg_options(class OptionParser *opp) { option_parser_register(opp, "-gpgpu_simd_model", OPT_INT32, &model, - "1 = post-dominator", "1"); + "1 = post-dominator, 2 = AWARE reconvergence (ITS)", + "1"); + option_parser_register(opp, "-gpgpu_simd_rec_time_out", OPT_INT32, + &rec_time_out, + "reconvergence timeout (-1 = disabled)", "-1"); + option_parser_register(opp, "-gpgpu_simd_rec_size", OPT_INT32, + &num_rec_entries, + "number of physical reconvergence table entries", + "32"); + option_parser_register(opp, "-gpgpu_simd_st_size", OPT_INT32, + &num_st_entries, + "number of physical splits table entries", "32"); + option_parser_register(opp, "-gpgpu_simd_rec_replacement", OPT_INT32, + &rec_replacement, + "reconvergence table replacement policy (1 = LRU)", + "1"); + option_parser_register(opp, "-gpgpu_simd_st_replacement", OPT_INT32, + &st_replacement, + "splits table replacement policy (1 = FIFO_BACK)", + "1"); option_parser_register( opp, "-gpgpu_shader_core_pipeline", OPT_CSTR, &gpgpu_shader_core_pipeline_opt, -- cgit v1.3