From b2def455d573f66fbc38dabda4adbc3a56225910 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Sun, 9 Feb 2020 20:39:22 -0500 Subject: adding kepler sass, skip-first-kernel and update config file --- src/gpgpu-sim/gpu-sim.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/gpgpu-sim/gpu-sim.cc') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 7f9985e..4e38f67 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -573,6 +573,9 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) option_parser_register(opp, "-trace_driven_mode", OPT_BOOL, &trace_driven_mode, "Turn on trace_driven_mode", "0"); + option_parser_register(opp, "-trace_skip_first_kernel", OPT_BOOL, + &trace_skip_first_kernel, "skip first intiliztion kernel in trace mode", + "0"); option_parser_register(opp, "-trace", OPT_CSTR, &g_traces_filename, "traces kernel file" "traces kernel file directory", -- cgit v1.3 From ed97d2a5b0096fb8afa4bc83fe2df515b2a2399c Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Tue, 31 Mar 2020 13:00:34 -0400 Subject: adding inst fetch throughput --- src/gpgpu-sim/gpu-sim.cc | 4 +++- src/gpgpu-sim/shader.cc | 9 +++++---- src/gpgpu-sim/shader.h | 1 + 3 files changed, 9 insertions(+), 5 deletions(-) (limited to 'src/gpgpu-sim/gpu-sim.cc') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 4e38f67..4ef9a7d 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -470,7 +470,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-perfect_inst_const_cache", OPT_BOOL, &perfect_inst_const_cache, "perfect inst and const cache mode, so all inst and const hits in the cache(default = disabled)", "0"); - + option_parser_register(opp, "-inst_fetch_throughput", OPT_INT32, &inst_fetch_throughput, + "the number of fetched intruction per warp each cycle", + "1"); } void gpgpu_sim_config::reg_options(option_parser_t opp) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index a2850d0..297f3bc 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3175,10 +3175,9 @@ void shader_core_ctx::cycle() execute(); read_operands(); issue(); - for(int i=0; i<8; ++i) { - decode(); - fetch(); - printf("Hello! \n"); + for(int i=0; i< m_config->inst_fetch_throughput; ++i) { + decode(); + fetch(); } } @@ -3235,6 +3234,7 @@ std::list opndcoll_rfu_t::arbiter_t::allocate_reads() ///// wavefront allocator from booksim... ---> // Loop through diagonals of request matrix + printf("####\n"); for ( int p = 0; p < _square; ++p ) { output = ( _pri + p ) % _square; @@ -3250,6 +3250,7 @@ std::list opndcoll_rfu_t::arbiter_t::allocate_reads() // Grant! _inmatch[input] = output; _outmatch[output] = input; + printf("Register File: granting banks %d to OC % \n", input, output); } output = ( output + 1 ) % _square; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index d41c220..43c448b 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1524,6 +1524,7 @@ class shader_core_config : public core_config bool gpgpu_concurrent_kernel_sm; bool perfect_inst_const_cache; + unsigned inst_fetch_throughput; }; -- cgit v1.3 From 3633eacca183608fe1a666212ba468b787c063a5 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Tue, 31 Mar 2020 20:43:41 -0400 Subject: adding new comments --- src/gpgpu-sim/gpu-sim.cc | 3 +++ src/gpgpu-sim/shader.cc | 13 +++++++------ src/gpgpu-sim/shader.h | 1 + 3 files changed, 11 insertions(+), 6 deletions(-) (limited to 'src/gpgpu-sim/gpu-sim.cc') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 4ef9a7d..94ea6d2 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -473,6 +473,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-inst_fetch_throughput", OPT_INT32, &inst_fetch_throughput, "the number of fetched intruction per warp each cycle", "1"); + option_parser_register(opp, "-gpgpu_reg_file_port_throughput", OPT_INT32, ®_file_port_throughput, + "the number ports of the register file", + "1"); } void gpgpu_sim_config::reg_options(option_parser_t opp) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index d9f7b94..ed0c25e 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -384,12 +384,12 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_fu.push_back(new dp_unit( &m_pipeline_reg[EX_WB], m_config, this )); m_dispatch_port.push_back(ID_OC_DP); m_issue_port.push_back(OC_EX_DP); - } + } for (int k = 0; k < m_config->gpgpu_num_int_units; k++) { m_fu.push_back(new int_unit( &m_pipeline_reg[EX_WB], m_config, this )); m_dispatch_port.push_back(ID_OC_INT); m_issue_port.push_back(OC_EX_INT); - } + } for (int k = 0; k < m_config->gpgpu_num_sfu_units; k++) { m_fu.push_back(new sfu( &m_pipeline_reg[EX_WB], m_config, this )); @@ -2413,7 +2413,8 @@ void ldst_unit::issue( register_set ®_set ) void ldst_unit::cycle() { writeback(); - m_operand_collector->step(); + for(int i=0; i< m_config->reg_file_port_throughput; ++i) + m_operand_collector->step(); for( unsigned stage=0; (stage+1)empty() && !m_pipeline_reg[stage+1]->empty() ) move_warp(m_pipeline_reg[stage], m_pipeline_reg[stage+1]); @@ -3234,7 +3235,7 @@ std::list opndcoll_rfu_t::arbiter_t::allocate_reads() ///// wavefront allocator from booksim... ---> // Loop through diagonals of request matrix - printf("####\n"); + // printf("####\n"); for ( int p = 0; p < _square; ++p ) { output = ( _pri + p ) % _outputs; @@ -3245,12 +3246,12 @@ std::list opndcoll_rfu_t::arbiter_t::allocate_reads() assert( output < _outputs ); if ( ( output < _outputs ) && ( _inmatch[input] == -1 ) && - ( _outmatch[output] == -1 ) && + //( _outmatch[output] == -1 ) && //allow OC to read multiple reg banks at the same cycle ( _request[input][output]/*.label != -1*/ ) ) { // Grant! _inmatch[input] = output; _outmatch[output] = input; - printf("Register File: granting bank %d to OC %d, schedid %d, warpid %d, Regid %d\n", input, output, (m_queue[input].front()).get_sid(), (m_queue[input].front()).get_wid(), (m_queue[input].front()).get_reg()); + // printf("Register File: granting bank %d to OC %d, schedid %d, warpid %d, Regid %d\n", input, output, (m_queue[input].front()).get_sid(), (m_queue[input].front()).get_wid(), (m_queue[input].front()).get_reg()); } output = ( output + 1 ) % _outputs; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 43c448b..665e3a5 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1525,6 +1525,7 @@ class shader_core_config : public core_config bool perfect_inst_const_cache; unsigned inst_fetch_throughput; + unsigned reg_file_port_throughput; }; -- cgit v1.3 From bd647361e2b8eb2d72f0055df851fcdee53e94cc Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Tue, 31 Mar 2020 20:54:44 -0400 Subject: fixing the tensor unit failing --- src/gpgpu-sim/gpu-sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gpgpu-sim/gpu-sim.cc') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 94ea6d2..e5b9c9d 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -453,7 +453,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "1"); option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32, &gpgpu_num_tensor_core_units, "Number of tensor_core units (default=1)", - "1"); + "0"); option_parser_register(opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units, "Number if ldst units (default=1) WARNING: not hooked up to anything", "1"); -- cgit v1.3 From 52204ff08a9c9a21a99fee3f976d2a419c014fec Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Mon, 18 May 2020 21:49:34 -0400 Subject: fixing some failing apps --- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 6 +++--- configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config | 4 ++-- src/gpgpu-sim/gpu-sim.cc | 3 ++- src/gpgpu-sim/shader.cc | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) (limited to 'src/gpgpu-sim/gpu-sim.cc') diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index e8329dd..b89971e 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -33,9 +33,9 @@ # volta clock domains #-gpgpu_clock_domains ::: --gpgpu_clock_domains 1365.0:1365.0:1365.0:7000.0 +-gpgpu_clock_domains 1365.0:1365.0:1365.0:3500.0 # boost mode -# -gpgpu_clock_domains 1680.0:1680.0:1680.0:7000.0 +# -gpgpu_clock_domains 1680.0:1680.0:1680.0:3500.0 # shader core pipeline config -gpgpu_shader_registers 65536 @@ -156,7 +156,7 @@ -gpgpu_n_mem_per_ctrlr 1 -gpgpu_dram_buswidth 2 -gpgpu_dram_burst_length 16 --dram_data_command_freq_ratio 2 # GDDR6 is configured as DDR in Turing +-dram_data_command_freq_ratio 4 -gpgpu_mem_address_mask 1 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS diff --git a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config index 0255f76..0df3eec 100644 --- a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config @@ -74,8 +74,8 @@ -ptx_opcode_initiation_dp 4,4,4,4,130 -ptx_opcode_latency_sfu 100 -ptx_opcode_initiation_sfu 8 --ptx_opcode_latency_tesnor 6 --ptx_opcode_initiation_tensor 2 +-ptx_opcode_latency_tesnor 8 +-ptx_opcode_initiation_tensor 4 # Volta has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index e5b9c9d..cd5fa56 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1828,7 +1828,8 @@ void shader_core_ctx::dump_warp_state( FILE *fout ) const void gpgpu_sim::perf_memcpy_to_gpu( size_t dst_start_addr, size_t count ) { if (m_memory_config->m_perf_sim_memcpy) { - assert (dst_start_addr % 32 == 0); + //if(!m_config.trace_driven_mode) //in trace-driven mode, CUDA runtime can start nre data structure at any position + // assert (dst_start_addr % 32 == 0); for ( unsigned counter = 0; counter < count; counter += 32 ) { const unsigned wr_addr = dst_start_addr + counter; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index ed0c25e..65ec113 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3091,7 +3091,7 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const case VOLTA: { //For Volta, we assign the remaining shared memory to L1 cache //For more info about adaptive cache, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x - assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared + //assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared //To Do: make it flexible and not tuned to 9KB share memory unsigned max_assoc = m_L1D_config.get_max_assoc(); -- cgit v1.3