From 687fa4c9e8e5b9e9ac60375b98d55daaf2d9c551 Mon Sep 17 00:00:00 2001 From: Ayub Gubran Date: Mon, 11 Feb 2013 20:05:03 -0800 Subject: bug31 1. Renaming '-gpgpu_dram_sched_queue_size' to '-gpgpu_frfcfs_dram_sched_queue_size' 2. Updating the output not print that statistic out at all if the DRAM access scheduler is FIFO. 3. Adding "-gpgpu_dram_return_queue_size" option to specify the return queue size (defualt 1024). config files should take this change into account [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15227] --- src/gpgpu-sim/gpu-sim.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/gpgpu-sim/gpu-sim.cc') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index ff5427a..3fa1d75 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -164,7 +164,10 @@ void memory_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_memlatency_stat", OPT_INT32, &gpgpu_memlatency_stat, "track and display latency statistics 0x2 enables MC, 0x4 enables queue logs", "0"); - option_parser_register(opp, "-gpgpu_dram_sched_queue_size", OPT_INT32, &gpgpu_dram_sched_queue_size, + option_parser_register(opp, "-gpgpu_frfcfs_dram_sched_queue_size", OPT_INT32, &gpgpu_frfcfs_dram_sched_queue_size, + "0 = unlimited (default); # entries per chip", + "0"); + option_parser_register(opp, "-gpgpu_dram_return_queue_size", OPT_INT32, &gpgpu_dram_return_queue_size, "0 = unlimited (default); # entries per chip", "0"); option_parser_register(opp, "-gpgpu_dram_buswidth", OPT_UINT32, &busW, -- cgit v1.3