From b577cbcdf229a2c02d1bf8584c6e82be7a14cb33 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sat, 16 Oct 2010 17:30:52 -0800 Subject: 1. creating cache_config object to encapsulate cache configuration information (and parse it before creating the simulator objects). 2. creating core_config to hold only features of a shader_core that are high level enough either (a) the functional simulator needs to know about them, or (b) they affect memory *access* generation. 3. in config files only (so far) separate out notion of write-{through,back}, from notion of when a line is allocated... will use this to distinguish different types of caches. passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7870] --- src/gpgpu-sim/gpu-sim.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'src/gpgpu-sim/gpu-sim.h') diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 762cea2..b881806 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -71,6 +71,8 @@ #include "../abstract_hardware_model.h" #include "addrdec.h" +#include "gpu-cache.h" +#include "shader.h" #include #include @@ -106,7 +108,7 @@ enum dram_ctrl_t { struct memory_config { memory_config() { - gpgpu_cache_dl2_opt=NULL; + m_valid = false; gpgpu_dram_timing_opt=NULL; gpgpu_L2_queue_config=NULL; } @@ -117,9 +119,13 @@ struct memory_config { tRCDWR = tRCD-(WL+1); tRTW = (CL+(BL/2)+2-WL); m_address_mapping.init(m_n_mem); + m_L2_config.init(); + m_valid = true; } - char *gpgpu_cache_dl2_opt; + bool m_valid; + cache_config m_L2_config; + char *gpgpu_dram_timing_opt; char *gpgpu_L2_queue_config; bool gpgpu_l2_readoverwrite; -- cgit v1.3