From b09eeed6aa36239f661d6452e996e3e5f8ef5984 Mon Sep 17 00:00:00 2001 From: Tayler Hetherington Date: Wed, 19 Sep 2012 14:51:45 -0800 Subject: Revision #2 of modifying the cache hierarchy. Separated the L1 and L2 cache access() implementations. Removed PRIVATE/SHARED cache scope configurations. Added WRITE_EVICT cache write policy. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14109] --- src/gpgpu-sim/l2cache.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gpgpu-sim/l2cache.cc') diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index a580052..c03c47f 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -74,7 +74,7 @@ memory_partition_unit::memory_partition_unit( unsigned partition_id, m_mf_allocator = new partition_mf_allocator(config); if(!m_config->m_L2_config.disabled()) - m_L2cache = new data_cache(L2c_name,m_config->m_L2_config,-1,-1,m_L2interface,m_mf_allocator,IN_PARTITION_L2_MISS_QUEUE); + m_L2cache = new l2_cache(L2c_name,m_config->m_L2_config,-1,-1,m_L2interface,m_mf_allocator,IN_PARTITION_L2_MISS_QUEUE); unsigned int icnt_L2; unsigned int L2_dram; -- cgit v1.3