From 8c81c1d04e8d20b08f122a12ce090b4f926adb4c Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 22 Aug 2018 10:19:52 -0400 Subject: adding lazy-fetch-on-read and invalidate operation to cache --- src/gpgpu-sim/l2cache.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/gpgpu-sim/l2cache.h') diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index 2d13918..18c0a8b 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -162,6 +162,7 @@ public: void set_done( mem_fetch *mf ); unsigned flushL2(); + unsigned invalidateL2(); // interface to L2_dram_queue bool L2_dram_queue_empty() const; -- cgit v1.3 From 13f07a2c820422db7e4e88e43d692dfe8e1b8cad Mon Sep 17 00:00:00 2001 From: Nick Date: Tue, 19 Feb 2019 18:40:45 -0500 Subject: Add initial infrastrucutre to support L2 (and other) cache statistics for AerialVision --- src/gpgpu-sim/gpu-cache.cc | 80 ++++++++++++++++++++++++++++++++++++++++++++++ src/gpgpu-sim/gpu-cache.h | 14 ++++++++ src/gpgpu-sim/gpu-sim.cc | 7 ++++ src/gpgpu-sim/l2cache.cc | 5 +++ src/gpgpu-sim/l2cache.h | 3 ++ 5 files changed, 109 insertions(+) (limited to 'src/gpgpu-sim/l2cache.h') diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index ba81440..d050946 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -600,9 +600,11 @@ void mshr_table::display( FILE *fp ) const{ /***************************************************************** Caches *****************************************************************/ cache_stats::cache_stats(){ m_stats.resize(NUM_MEM_ACCESS_TYPE); + m_stats_pw.resize(NUM_MEM_ACCESS_TYPE); m_fail_stats.resize(NUM_MEM_ACCESS_TYPE); for(unsigned i=0; iget_access_type(), m_stats.select_stats_status(status, cache_status)); + m_stats.inc_stats_pw(mf->get_access_type(), m_stats.select_stats_status(status, cache_status)); return cache_status; } @@ -1575,6 +1652,8 @@ data_cache::access( new_addr_type addr, = process_tag_probe( wr, probe_status, addr, cache_index, mf, time, events ); m_stats.inc_stats(mf->get_access_type(), m_stats.select_stats_status(probe_status, access_status)); + m_stats.inc_stats_pw(mf->get_access_type(), + m_stats.select_stats_status(probe_status, access_status)); return access_status; } @@ -1639,6 +1718,7 @@ enum cache_request_status tex_cache::access( new_addr_type addr, mem_fetch *mf, cache_status = HIT_RESERVED; } m_stats.inc_stats(mf->get_access_type(), m_stats.select_stats_status(status, cache_status)); + m_stats.inc_stats_pw(mf->get_access_type(), m_stats.select_stats_status(status, cache_status)); return cache_status; } diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index e663cf6..c1061ef 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -978,7 +978,11 @@ class cache_stats { public: cache_stats(); void clear(); + // Clear AerialVision cache stats after each window + void clear_pw(); void inc_stats(int access_type, int access_outcome); + // Increment AerialVision cache stats + void inc_stats_pw(int access_type, int access_outcome); void inc_fail_stats(int access_type, int fail_outcome); enum cache_request_status select_stats_status(enum cache_request_status probe, enum cache_request_status access) const; unsigned &operator()(int access_type, int access_outcome, bool fail_outcome); @@ -991,12 +995,18 @@ public: unsigned get_stats(enum mem_access_type *access_type, unsigned num_access_type, enum cache_request_status *access_status, unsigned num_access_status) const; void get_sub_stats(struct cache_sub_stats &css) const; + // Get per-window cache stats for AerialVision + unsigned get_stats_pw(enum mem_access_type *access_type, unsigned num_access_type, enum cache_request_status *access_status, unsigned num_access_status) const; + void get_sub_stats_pw(struct cache_sub_stats &css) const; + void sample_cache_port_utility(bool data_port_busy, bool fill_port_busy); private: bool check_valid(int type, int status) const; bool check_fail_valid(int type, int fail) const; std::vector< std::vector > m_stats; + // AerialVision cache stats (per-window) + std::vector< std::vector > m_stats_pw; std::vector< std::vector > m_fail_stats; unsigned long long m_cache_port_available_cycles; @@ -1082,6 +1092,10 @@ public: void get_sub_stats(struct cache_sub_stats &css) const { m_stats.get_sub_stats(css); } + // Per-window sub stats for AerialVision support + void get_sub_stats_pw(struct cache_sub_stats &css) const { + m_stats.get_sub_stats_pw(css); + } // accessors for cache bandwidth availability bool data_port_free() const { return m_bandwidth_management.data_port_free(); } diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index ec570bf..c253367 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1148,6 +1148,9 @@ void gpgpu_sim::gpu_print_stat() cache_stats l2_stats; struct cache_sub_stats l2_css; struct cache_sub_stats total_l2_css; + cache_stats l2_stats_pw; + struct cache_sub_stats l2_css_pw; + struct cache_sub_stats total_l2_css_pw; l2_stats.clear(); l2_css.clear(); total_l2_css.clear(); @@ -1156,11 +1159,15 @@ void gpgpu_sim::gpu_print_stat() for (unsigned i=0;im_n_mem_sub_partition;i++){ m_memory_sub_partition[i]->accumulate_L2cache_stats(l2_stats); m_memory_sub_partition[i]->get_L2cache_sub_stats(l2_css); + m_memory_sub_partition[i]->get_L2cache_sub_stats_pw(l2_css_pw); fprintf( stdout, "L2_cache_bank[%d]: Access = %u, Miss = %u, Miss_rate = %.3lf, Pending_hits = %u, Reservation_fails = %u\n", i, l2_css.accesses, l2_css.misses, (double)l2_css.misses / (double)l2_css.accesses, l2_css.pending_hits, l2_css.res_fails); + fprintf( stdout, "L2_cache_bank[%d]: Access = %u, Miss = %u, Miss_rate = %.3lf, Pending_hits = %u, Reservation_fails = %u\n", + i, l2_css_pw.accesses, l2_css_pw.misses, (double)l2_css_pw.misses / (double)l2_css_pw.accesses, l2_css_pw.pending_hits, l2_css_pw.res_fails); total_l2_css += l2_css; + total_l2_css_pw += l2_css_pw; } if (!m_memory_config->m_L2_config.disabled() && m_memory_config->m_L2_config.get_num_lines()) { //L2c_print_cache_stat(); diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index 25da107..a662446 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -718,6 +718,11 @@ void memory_sub_partition::get_L2cache_sub_stats(struct cache_sub_stats &css) co } } +void memory_sub_partition::get_L2cache_sub_stats_pw(struct cache_sub_stats &css) const{ + if (!m_config->m_L2_config.disabled()) { + m_L2cache->get_sub_stats_pw(css); + } +} void memory_sub_partition::visualizer_print( gzFile visualizer_file ) { // TODO: Add visualizer stats for L2 cache diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index 18c0a8b..57f3e94 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -180,6 +180,9 @@ public: void accumulate_L2cache_stats(class cache_stats &l2_stats) const; void get_L2cache_sub_stats(struct cache_sub_stats &css) const; + // Support for getting per-window L2 stats for AerialVision + void get_L2cache_sub_stats_pw(struct cache_sub_stats &css) const; + void force_l2_tag_update(new_addr_type addr, unsigned time, mem_access_sector_mask_t mask) { m_L2cache->force_tag_access( addr, m_memcpy_cycle_offset + time, mask ); -- cgit v1.3 From c1833f27cdd0ad7d41afc64db0ec693571080c05 Mon Sep 17 00:00:00 2001 From: Nick Date: Wed, 20 Feb 2019 13:46:20 -0500 Subject: Add full support for deprecated AerialVision L2 stats --- src/gpgpu-sim/gpu-cache.cc | 67 +++++++++++++++++++------------------ src/gpgpu-sim/gpu-cache.h | 69 +++++++++++++++++++++++++++++++++++++-- src/gpgpu-sim/gpu-sim.cc | 8 +---- src/gpgpu-sim/l2cache.cc | 38 +++++++++++++++++---- src/gpgpu-sim/l2cache.h | 3 +- src/gpgpu-sim/mem_latency_stat.cc | 6 ++++ src/gpgpu-sim/mem_latency_stat.h | 8 +++++ 7 files changed, 147 insertions(+), 52 deletions(-) (limited to 'src/gpgpu-sim/l2cache.h') diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index d050946..0ef6452 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -769,11 +769,7 @@ void cache_stats::print_stats(FILE *fout, const char *cache_name) const{ mem_access_type_str((enum mem_access_type)type), cache_request_status_str((enum cache_request_status)status), m_stats[type][status]); - fprintf(fout, "\t%s[%s][%s] = %u\n", - m_cache_name.c_str(), - mem_access_type_str((enum mem_access_type)type), - cache_request_status_str((enum cache_request_status)status), - m_stats_pw[type][status]); + if(status != RESERVATION_FAIL) total_access[type]+= m_stats[type][status]; } @@ -834,23 +830,6 @@ unsigned cache_stats::get_stats(enum mem_access_type *access_type, unsigned num_ return total; } -unsigned cache_stats::get_stats_pw(enum mem_access_type *access_type, unsigned num_access_type, enum cache_request_status *access_status, unsigned num_access_status) const{ - /// - /// Returns a sum of the stats corresponding to each "access_type" and "access_status" pair. - /// "access_type" is an array of "num_access_type" mem_access_types. - /// "access_status" is an array of "num_access_status" cache_request_statuses. - /// - unsigned total=0; - for(unsigned type =0; type < num_access_type; ++type){ - for(unsigned status=0; status < num_access_status; ++status){ - if(!check_valid((int)access_type[type], (int)access_status[status])) - assert(0 && "Unknown cache access type or access outcome"); - total += m_stats_pw[access_type[type]][access_status[status]]; - } - } - return total; -} - void cache_stats::get_sub_stats(struct cache_sub_stats &css) const{ /// /// Overwrites "css" with the appropriate statistics from this cache. @@ -881,11 +860,11 @@ void cache_stats::get_sub_stats(struct cache_sub_stats &css) const{ css = t_css; } -void cache_stats::get_sub_stats_pw(struct cache_sub_stats &css) const{ +void cache_stats::get_sub_stats_pw(struct cache_sub_stats_pw &css) const{ /// /// Overwrites "css" with the appropriate statistics from this cache. /// - struct cache_sub_stats t_css; + struct cache_sub_stats_pw t_css; t_css.clear(); for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) { @@ -893,23 +872,43 @@ void cache_stats::get_sub_stats_pw(struct cache_sub_stats &css) const{ if(status == HIT || status == MISS || status == SECTOR_MISS || status == HIT_RESERVED) t_css.accesses += m_stats_pw[type][status]; - if(status == MISS || status == SECTOR_MISS) - t_css.misses += m_stats_pw[type][status]; + if(status == HIT){ + if(type == GLOBAL_ACC_R || type == CONST_ACC_R || type == INST_ACC_R){ + t_css.read_hits += m_stats_pw[type][status]; + } else if(type == GLOBAL_ACC_W){ + t_css.write_hits += m_stats_pw[type][status]; + } + } - if(status == HIT_RESERVED) - t_css.pending_hits += m_stats_pw[type][status]; + if(status == MISS || status == SECTOR_MISS){ + if(type == GLOBAL_ACC_R || type == CONST_ACC_R || type == INST_ACC_R){ + t_css.read_misses += m_stats_pw[type][status]; + } else if(type == GLOBAL_ACC_W){ + t_css.write_misses += m_stats_pw[type][status]; + } + } - if(status == RESERVATION_FAIL) - t_css.res_fails += m_stats_pw[type][status]; + if(status == HIT_RESERVED){ + if(type == GLOBAL_ACC_R || type == CONST_ACC_R || type == INST_ACC_R){ + t_css.read_pending_hits += m_stats_pw[type][status]; + } else if(type == GLOBAL_ACC_W){ + t_css.write_pending_hits += m_stats_pw[type][status]; + } + } + + if(status == RESERVATION_FAIL){ + if(type == GLOBAL_ACC_R || type == CONST_ACC_R || type == INST_ACC_R){ + t_css.read_res_fails += m_stats_pw[type][status]; + } else if(type == GLOBAL_ACC_W){ + t_css.write_res_fails += m_stats_pw[type][status]; + } + } } } - t_css.port_available_cycles = m_cache_port_available_cycles; - t_css.data_port_busy_cycles = m_cache_data_port_busy_cycles; - t_css.fill_port_busy_cycles = m_cache_fill_port_busy_cycles; - css = t_css; } + bool cache_stats::check_valid(int type, int status) const{ /// /// Verify a valid access_type/access_status diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index c1061ef..5449db7 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -968,6 +968,66 @@ struct cache_sub_stats{ void print_port_stats(FILE *fout, const char *cache_name) const; }; + +// Used for collecting AerialVision per-window statistics +struct cache_sub_stats_pw{ + unsigned accesses; + unsigned write_misses; + unsigned write_hits; + unsigned write_pending_hits; + unsigned write_res_fails; + + unsigned read_misses; + unsigned read_hits; + unsigned read_pending_hits; + unsigned read_res_fails; + + cache_sub_stats_pw(){ + clear(); + } + void clear(){ + accesses = 0; + write_misses = 0; + write_hits = 0; + write_pending_hits = 0; + write_res_fails = 0; + read_misses = 0; + read_hits = 0; + read_pending_hits = 0; + read_res_fails = 0; + } + cache_sub_stats_pw &operator+=(const cache_sub_stats_pw &css){ + /// + /// Overloading += operator to easily accumulate stats + /// + accesses += css.accesses; + write_misses += css.write_misses; + read_misses += css.read_misses; + write_pending_hits += css.write_pending_hits; + read_pending_hits += css.read_pending_hits; + write_res_fails += css.write_res_fails; + read_res_fails += css.read_res_fails; + return *this; + } + + cache_sub_stats_pw operator+(const cache_sub_stats_pw &cs){ + /// + /// Overloading + operator to easily accumulate stats + /// + cache_sub_stats_pw ret; + ret.accesses = accesses + cs.accesses; + ret.write_misses = write_misses + cs.write_misses; + ret.read_misses = read_misses + cs.read_misses; + ret.write_pending_hits = write_pending_hits + cs.write_pending_hits; + ret.read_pending_hits = read_pending_hits + cs.read_pending_hits; + ret.write_res_fails = write_res_fails + cs.write_res_fails; + ret.read_res_fails = read_res_fails + cs.read_res_fails; + return ret; + } + +}; + + /// /// Cache_stats /// Used to record statistics for each cache. @@ -996,8 +1056,7 @@ public: void get_sub_stats(struct cache_sub_stats &css) const; // Get per-window cache stats for AerialVision - unsigned get_stats_pw(enum mem_access_type *access_type, unsigned num_access_type, enum cache_request_status *access_status, unsigned num_access_status) const; - void get_sub_stats_pw(struct cache_sub_stats &css) const; + void get_sub_stats_pw(struct cache_sub_stats_pw &css) const; void sample_cache_port_utility(bool data_port_busy, bool fill_port_busy); private: @@ -1092,8 +1151,12 @@ public: void get_sub_stats(struct cache_sub_stats &css) const { m_stats.get_sub_stats(css); } + // Clear per-window stats for AerialVision support + void clear_pw(){ + m_stats.clear_pw(); + } // Per-window sub stats for AerialVision support - void get_sub_stats_pw(struct cache_sub_stats &css) const { + void get_sub_stats_pw(struct cache_sub_stats_pw &css) const { m_stats.get_sub_stats_pw(css); } diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index c253367..56b9681 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -917,6 +917,7 @@ void gpgpu_sim::update_stats() { void gpgpu_sim::print_stats() { ptx_file_line_stats_write_file(); + visualizer_printstat(); gpu_print_stat(); if (g_network_mode) { @@ -1148,9 +1149,6 @@ void gpgpu_sim::gpu_print_stat() cache_stats l2_stats; struct cache_sub_stats l2_css; struct cache_sub_stats total_l2_css; - cache_stats l2_stats_pw; - struct cache_sub_stats l2_css_pw; - struct cache_sub_stats total_l2_css_pw; l2_stats.clear(); l2_css.clear(); total_l2_css.clear(); @@ -1159,15 +1157,11 @@ void gpgpu_sim::gpu_print_stat() for (unsigned i=0;im_n_mem_sub_partition;i++){ m_memory_sub_partition[i]->accumulate_L2cache_stats(l2_stats); m_memory_sub_partition[i]->get_L2cache_sub_stats(l2_css); - m_memory_sub_partition[i]->get_L2cache_sub_stats_pw(l2_css_pw); fprintf( stdout, "L2_cache_bank[%d]: Access = %u, Miss = %u, Miss_rate = %.3lf, Pending_hits = %u, Reservation_fails = %u\n", i, l2_css.accesses, l2_css.misses, (double)l2_css.misses / (double)l2_css.accesses, l2_css.pending_hits, l2_css.res_fails); - fprintf( stdout, "L2_cache_bank[%d]: Access = %u, Miss = %u, Miss_rate = %.3lf, Pending_hits = %u, Reservation_fails = %u\n", - i, l2_css_pw.accesses, l2_css_pw.misses, (double)l2_css_pw.misses / (double)l2_css_pw.accesses, l2_css_pw.pending_hits, l2_css_pw.res_fails); total_l2_css += l2_css; - total_l2_css_pw += l2_css_pw; } if (!m_memory_config->m_L2_config.disabled() && m_memory_config->m_L2_config.get_num_lines()) { //L2c_print_cache_stat(); diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index a662446..0237525 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -519,14 +519,23 @@ void memory_sub_partition::print( FILE *fp ) const void memory_stats_t::visualizer_print( gzFile visualizer_file ) { - // gzprintf(visualizer_file, "Ltwowritemiss: %d\n", L2_write_miss); - // gzprintf(visualizer_file, "Ltwowritehit: %d\n", L2_write_access-L2_write_miss); - // gzprintf(visualizer_file, "Ltworeadmiss: %d\n", L2_read_miss); - // gzprintf(visualizer_file, "Ltworeadhit: %d\n", L2_read_access-L2_read_miss); + gzprintf(visualizer_file, "Ltwowritemiss: %d\n", L2_write_miss); + gzprintf(visualizer_file, "Ltwowritehit: %d\n", L2_write_hit); + gzprintf(visualizer_file, "Ltworeadmiss: %d\n", L2_read_miss); + gzprintf(visualizer_file, "Ltworeadhit: %d\n", L2_read_hit); + clear_L2_stats_pw(); + if (num_mfs) gzprintf(visualizer_file, "averagemflatency: %lld\n", mf_total_lat/num_mfs); } +void memory_stats_t::clear_L2_stats_pw(){ + L2_write_miss = 0; + L2_write_hit = 0; + L2_read_miss = 0; + L2_read_hit = 0; +} + void gpgpu_sim::print_dram_stats(FILE *fout) const { unsigned cmd=0; @@ -718,13 +727,28 @@ void memory_sub_partition::get_L2cache_sub_stats(struct cache_sub_stats &css) co } } -void memory_sub_partition::get_L2cache_sub_stats_pw(struct cache_sub_stats &css) const{ +void memory_sub_partition::get_L2cache_sub_stats_pw(struct cache_sub_stats_pw &css) const{ if (!m_config->m_L2_config.disabled()) { m_L2cache->get_sub_stats_pw(css); } } + +void memory_sub_partition::clear_L2cache_stats_pw() { + if (!m_config->m_L2_config.disabled()) { + m_L2cache->clear_pw(); + } +} + void memory_sub_partition::visualizer_print( gzFile visualizer_file ) { - // TODO: Add visualizer stats for L2 cache -} + // TODO: Add visualizer stats for L2 cache + cache_sub_stats_pw temp_sub_stats; + get_L2cache_sub_stats_pw(temp_sub_stats); + m_stats->L2_read_miss += temp_sub_stats.read_misses; + m_stats->L2_write_miss += temp_sub_stats.write_misses; + m_stats->L2_read_hit += temp_sub_stats.read_hits; + m_stats->L2_write_hit += temp_sub_stats.write_hits; + + clear_L2cache_stats_pw(); +} diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index 57f3e94..beafdd3 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -181,7 +181,8 @@ public: void get_L2cache_sub_stats(struct cache_sub_stats &css) const; // Support for getting per-window L2 stats for AerialVision - void get_L2cache_sub_stats_pw(struct cache_sub_stats &css) const; + void get_L2cache_sub_stats_pw(struct cache_sub_stats_pw &css) const; + void clear_L2cache_stats_pw(); void force_l2_tag_update(new_addr_type addr, unsigned time, mem_access_sector_mask_t mask) { diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc index c5452b9..49abae4 100644 --- a/src/gpgpu-sim/mem_latency_stat.cc +++ b/src/gpgpu-sim/mem_latency_stat.cc @@ -129,6 +129,12 @@ memory_stats_t::memory_stats_t( unsigned n_shader, const struct shader_core_conf } } + // AerialVision L2 stats + L2_read_miss = 0; + L2_write_miss = 0; + L2_read_hit = 0; + L2_write_hit = 0; + L2_cbtoL2length = (unsigned int*) calloc(mem_config->m_n_mem, sizeof(unsigned int)); L2_cbtoL2writelength = (unsigned int*) calloc(mem_config->m_n_mem, sizeof(unsigned int)); L2_L2tocblength = (unsigned int*) calloc(mem_config->m_n_mem, sizeof(unsigned int)); diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h index 5b89202..982b9ae 100644 --- a/src/gpgpu-sim/mem_latency_stat.h +++ b/src/gpgpu-sim/mem_latency_stat.h @@ -47,6 +47,9 @@ public: void visualizer_print( gzFile visualizer_file ); + // Reset local L2 stats that are aggregated each sampling window + void clear_L2_stats_pw(); + unsigned m_n_shader; const struct shader_core_config *m_shader_config; @@ -84,6 +87,11 @@ public: unsigned ***mem_access_type_stats; // dram access type classification + // AerialVision L2 stats + unsigned L2_read_miss; + unsigned L2_write_miss; + unsigned L2_read_hit; + unsigned L2_write_hit; // L2 cache stats unsigned int *L2_cbtoL2length; -- cgit v1.3 From 21d937256fbca004c926531cfef1adefcedeef91 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 29 Jul 2019 21:15:59 -0400 Subject: adding simple dram model --- src/gpgpu-sim/gpu-sim.cc | 7 ++++- src/gpgpu-sim/gpu-sim.h | 1 + src/gpgpu-sim/l2cache.cc | 77 ++++++++++++++++++++++++++++++++++++++++++------ src/gpgpu-sim/l2cache.h | 1 + 4 files changed, 76 insertions(+), 10 deletions(-) (limited to 'src/gpgpu-sim/l2cache.h') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 343ff86..92d5366 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -156,6 +156,8 @@ void memory_config::reg_options(class OptionParser * opp) { option_parser_register(opp, "-perf_sim_memcpy", OPT_BOOL, &m_perf_sim_memcpy, "Fill the L2 cache on memcpy", "1"); + option_parser_register(opp, "-simple_dram_model", OPT_BOOL, &simple_dram_model, + "simple_dram_model with fixed latency and BW", "0"); option_parser_register(opp, "-gpgpu_dram_scheduler", OPT_INT32, &scheduler_type, "0 = fifo, 1 = FR-FCFS (defaul)", "1"); option_parser_register(opp, "-gpgpu_dram_partition_queues", OPT_CSTR, &gpgpu_L2_queue_config, @@ -1606,7 +1608,10 @@ void gpgpu_sim::cycle() if (clock_mask & DRAM) { for (unsigned i=0;im_n_mem;i++){ - m_memory_partition_unit[i]->dram_cycle(); // Issue the dram command (scheduler + delay model) + if(m_memory_config->simple_dram_model) + m_memory_partition_unit[i]->simple_dram_model_cycle(); + else + m_memory_partition_unit[i]->dram_cycle(); // Issue the dram command (scheduler + delay model) // Update performance counters for DRAM m_memory_partition_unit[i]->set_dram_power_stats(m_power_stats->pwr_mem_stat->n_cmd[CURRENT_STAT_IDX][i], m_power_stats->pwr_mem_stat->n_activity[CURRENT_STAT_IDX][i], m_power_stats->pwr_mem_stat->n_nop[CURRENT_STAT_IDX][i], m_power_stats->pwr_mem_stat->n_act[CURRENT_STAT_IDX][i], m_power_stats->pwr_mem_stat->n_pre[CURRENT_STAT_IDX][i], diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index e98e499..c14d0a7 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -290,6 +290,7 @@ struct memory_config { unsigned write_high_watermark; unsigned write_low_watermark; bool m_perf_sim_memcpy; + bool simple_dram_model; }; // global counters and flags (please try not to add to this list!!!) diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index 0edc3b7..f24a596 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -203,7 +203,67 @@ int memory_partition_unit::global_sub_partition_id_to_local_id(int global_sub_pa return (global_sub_partition_id - m_id * m_config->m_n_sub_partition_per_memory_channel); } -void memory_partition_unit::dram_cycle() +void memory_partition_unit::simple_dram_model_cycle() +{ + + // pop completed memory request from dram and push it to dram-to-L2 queue + // of the original sub partition + if (!m_dram_latency_queue.empty() && ( (gpu_sim_cycle+gpu_tot_sim_cycle) >= m_dram_latency_queue.front().ready_cycle )) { + mem_fetch* mf_return = m_dram_latency_queue.front().req; + if( mf_return->get_access_type() != L1_WRBK_ACC && mf_return->get_access_type() != L2_WRBK_ACC ) { + mf_return->set_reply(); + + unsigned dest_global_spid = mf_return->get_sub_partition_id(); + int dest_spid = global_sub_partition_id_to_local_id(dest_global_spid); + assert(m_sub_partition[dest_spid]->get_id() == dest_global_spid); + if (!m_sub_partition[dest_spid]->dram_L2_queue_full()) { + if( mf_return->get_access_type() == L1_WRBK_ACC ) { + m_sub_partition[dest_spid]->set_done(mf_return); + delete mf_return; + } else { + m_sub_partition[dest_spid]->dram_L2_queue_push(mf_return); + mf_return->set_status(IN_PARTITION_DRAM_TO_L2_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); + m_arbitration_metadata.return_credit(dest_spid); + MEMPART_DPRINTF("mem_fetch request %p return from dram to sub partition %d\n", mf_return, dest_spid); + } + m_dram_latency_queue.pop_front(); + } + + } else { + this->set_done(mf_return); + delete mf_return; + m_dram_latency_queue.pop_front(); + } + } + + // mem_fetch *mf = m_sub_partition[spid]->L2_dram_queue_top(); + //if( !m_dram->full(mf->is_write()) ) { + // L2->DRAM queue to DRAM latency queue + // Arbitrate among multiple L2 subpartitions + int last_issued_partition = m_arbitration_metadata.last_borrower(); + for (unsigned p = 0; p < m_config->m_n_sub_partition_per_memory_channel; p++) { + int spid = (p + last_issued_partition + 1) % m_config->m_n_sub_partition_per_memory_channel; + if (!m_sub_partition[spid]->L2_dram_queue_empty() && can_issue_to_dram(spid)) { + mem_fetch *mf = m_sub_partition[spid]->L2_dram_queue_top(); + if(m_dram->full(mf->is_write()) ) + break; + + m_sub_partition[spid]->L2_dram_queue_pop(); + MEMPART_DPRINTF("Issue mem_fetch request %p from sub partition %d to dram\n", mf, spid); + dram_delay_t d; + d.req = mf; + d.ready_cycle = gpu_sim_cycle+gpu_tot_sim_cycle + m_config->dram_latency; + m_dram_latency_queue.push_back(d); + mf->set_status(IN_PARTITION_DRAM_LATENCY_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); + m_arbitration_metadata.borrow_credit(spid); + break; // the DRAM should only accept one request per cycle + } + } + //} + +} + +void memory_partition_unit::dram_cycle() { // pop completed memory request from dram and push it to dram-to-L2 queue // of the original sub partition @@ -228,8 +288,8 @@ void memory_partition_unit::dram_cycle() m_dram->return_queue_pop(); } - m_dram->cycle(); - m_dram->dram_log(SAMPLELOG); + m_dram->cycle(); + m_dram->dram_log(SAMPLELOG); // mem_fetch *mf = m_sub_partition[spid]->L2_dram_queue_top(); //if( !m_dram->full(mf->is_write()) ) { @@ -257,12 +317,11 @@ void memory_partition_unit::dram_cycle() //} // DRAM latency queue - - if( !m_dram_latency_queue.empty() && ( (gpu_sim_cycle+gpu_tot_sim_cycle) >= m_dram_latency_queue.front().ready_cycle ) && !m_dram->full(m_dram_latency_queue.front().req->is_write()) ) { - mem_fetch* mf = m_dram_latency_queue.front().req; - m_dram_latency_queue.pop_front(); - m_dram->push(mf); - } + if( !m_dram_latency_queue.empty() && ( (gpu_sim_cycle+gpu_tot_sim_cycle) >= m_dram_latency_queue.front().ready_cycle ) && !m_dram->full(m_dram_latency_queue.front().req->is_write()) ) { + mem_fetch* mf = m_dram_latency_queue.front().req; + m_dram_latency_queue.pop_front(); + m_dram->push(mf); + } } void memory_partition_unit::set_done( mem_fetch *mf ) diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index beafdd3..9a51c0e 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -65,6 +65,7 @@ public: void cache_cycle( unsigned cycle ); void dram_cycle(); + void simple_dram_model_cycle(); void set_done( mem_fetch *mf ); -- cgit v1.3