From 928f6d330516f03bdbecd52350bf1b9fb9fcf534 Mon Sep 17 00:00:00 2001
From: Inderpreet Singh <w6o6@ece.ubc.ca>
Date: Sun, 26 Feb 2012 03:55:38 -0800
Subject: Added fixed latency queue for modeling DRAM latency

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11521]
---
 src/gpgpu-sim/l2cache.h | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

(limited to 'src/gpgpu-sim/l2cache.h')

diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h
index 12663bd..22640b8 100644
--- a/src/gpgpu-sim/l2cache.h
+++ b/src/gpgpu-sim/l2cache.h
@@ -92,7 +92,15 @@ private:
     	unsigned long long ready_cycle;
     	class mem_fetch* req;
    };
-   std::queue<rop_delay_t> m_rop; 
+   std::queue<rop_delay_t> m_rop;
+
+   // model DRAM access scheduler latency (fixed latency between L2 and DRAM)
+   struct dram_delay_t
+   {
+      unsigned long long ready_cycle;
+      class mem_fetch* req;
+   };
+   std::queue<dram_delay_t> m_dram_latency_queue;
 
    // these are various FIFOs between units within a memory partition
    fifo_pipeline<mem_fetch> *m_icnt_L2_queue;
-- 
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