From ee5ea34857e4ecc6c63d4971e549076c6a9888ba Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Tue, 19 Oct 2010 23:10:51 -0800 Subject: adding texture cache model with fragment fifo for latency hiding passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7886] --- src/gpgpu-sim/l2cache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gpgpu-sim/l2cache.h') diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index 6900394..7d1a8b2 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -103,7 +103,7 @@ private: unsigned m_id; const struct memory_config *m_config; class dram_t *m_dram; - class cache_t *m_L2cache; + class read_only_cache *m_L2cache; class L2interface *m_L2interface; // model delay of ROP units with a fixed latency -- cgit v1.3