From 6e06c2e1de8c51a88845b7f35cea219dca7456f2 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sun, 28 Nov 2010 20:48:33 -0800 Subject: enabling L2 data cache... it is write through, write evict like L1. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8154] --- src/gpgpu-sim/mem_fetch.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gpgpu-sim/mem_fetch.cc') diff --git a/src/gpgpu-sim/mem_fetch.cc b/src/gpgpu-sim/mem_fetch.cc index f4c3bcc..699ba0a 100644 --- a/src/gpgpu-sim/mem_fetch.cc +++ b/src/gpgpu-sim/mem_fetch.cc @@ -92,7 +92,7 @@ mem_fetch::mem_fetch( const mem_access_t &access, m_wid = wid; config->m_address_mapping.addrdec_tlx(access.get_addr(),&m_raw_addr); m_partition_addr = config->m_address_mapping.partition_address(access.get_addr()); - m_type = m_access.is_write()?WR_REQ:RD_REQ; + m_type = m_access.is_write()?WRITE_REQUEST:READ_REQUEST; m_timestamp = gpu_sim_cycle + gpu_tot_sim_cycle; m_timestamp2 = 0; m_status = MEM_FETCH_INITIALIZED; -- cgit v1.3