From dc93f319051a9a9936a02cd9c1f7843a382a2da0 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Thu, 21 Oct 2010 07:16:49 -0800 Subject: 1. rewriting memory access generation code (from scratch), why not... passing CUDA 3.1 and ptxplus correlation, but correlation still bad (0.62)... after debugging 1 to get it working with ptxplus, problem is very clear: shared and constant cache accesses not occuring for operations that combine these with ALU operations. TODO: have a "read-operands" stage, which somehow combines operand collector register reading with shared and const memory accesses... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7895] --- src/gpgpu-sim/mem_latency_stat.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gpgpu-sim/mem_latency_stat.cc') diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc index f78717e..5b4d3ac 100644 --- a/src/gpgpu-sim/mem_latency_stat.cc +++ b/src/gpgpu-sim/mem_latency_stat.cc @@ -229,7 +229,7 @@ void memory_stats_t::memlatstat_dram_access(mem_fetch *mf) } if (mf->get_pc() != (unsigned)-1) ptx_file_line_stats_add_dram_traffic(mf->get_pc(),1); - mem_access_type_stats[mf->get_mem_acc()][dram_id][bank]++; + mem_access_type_stats[mf->get_access_type()][dram_id][bank]++; } } -- cgit v1.3