From 36ce0f2243fd0723a746b3c2f5f0651577312400 Mon Sep 17 00:00:00 2001 From: Tayler Hetherington Date: Fri, 30 Nov 2012 21:29:42 -0800 Subject: Merging Power model into Fermi //depot/gpgpu_sim_research/fermi_power/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723] --- src/gpgpu-sim/mem_latency_stat.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'src/gpgpu-sim/mem_latency_stat.h') diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h index 95017d8..83114fa 100644 --- a/src/gpgpu-sim/mem_latency_stat.h +++ b/src/gpgpu-sim/mem_latency_stat.h @@ -82,9 +82,9 @@ public: // stats + unsigned L2_write_access; unsigned L2_write_miss; - unsigned L2_write_hit; - unsigned L2_read_hit; + unsigned L2_read_access; unsigned L2_read_miss; unsigned int *L2_cbtoL2length; unsigned int *L2_cbtoL2writelength; @@ -98,6 +98,11 @@ public: unsigned int **row_access; //row_access[dram chip id][bank id] unsigned int **max_conc_access2samerow; //max_conc_access2samerow[dram chip id][bank id] unsigned int **max_servicetime2samerow; //max_servicetime2samerow[dram chip id][bank id] + + // Power stats + unsigned total_n_access; + unsigned total_n_reads; + unsigned total_n_writes; }; #endif /*MEM_LATENCY_STAT_H*/ -- cgit v1.3