From 58459bf7a55010eccf9940cfdb53cbc854b0989c Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sat, 16 Oct 2010 11:59:28 -0800 Subject: 1. moving address decoding into a class (and out of cache entirely) 2. moving DRAM timing parameters into memory_config class 3. removing some likely useless statistics 4. other cleaning up of code passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7868] --- src/gpgpu-sim/mem_latency_stat.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'src/gpgpu-sim/mem_latency_stat.h') diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h index c2a09b7..14868ef 100644 --- a/src/gpgpu-sim/mem_latency_stat.h +++ b/src/gpgpu-sim/mem_latency_stat.h @@ -72,8 +72,7 @@ class memory_stats_t { public: - memory_stats_t( unsigned n_mem, - unsigned n_shader, + memory_stats_t( unsigned n_shader, struct shader_core_config *shader_config, struct memory_config *mem_config ); @@ -88,7 +87,6 @@ public: void print( FILE *fp ); - unsigned m_n_mem; unsigned m_n_shader; const struct shader_core_config *m_shader_config; @@ -139,6 +137,12 @@ public: unsigned int *L2_dramtoL2length; unsigned int *L2_dramtoL2writelength; unsigned int *L2_L2todramlength; + + unsigned int **concurrent_row_access; //concurrent_row_access[dram chip id][bank id] + unsigned int **num_activates; //num_activates[dram chip id][bank id] + unsigned int **row_access; //row_access[dram chip id][bank id] + unsigned int **max_conc_access2samerow; //max_conc_access2samerow[dram chip id][bank id] + unsigned int **max_servicetime2samerow; //max_servicetime2samerow[dram chip id][bank id] }; #endif /*MEM_LATENCY_STAT_H*/ -- cgit v1.3