From 84c6cf45131e42b1a724ebf7977987a9ddb70db9 Mon Sep 17 00:00:00 2001 From: VijayKandiah Date: Sun, 17 Oct 2021 02:18:10 -0500 Subject: AccelWattch dev Integration --- src/gpgpu-sim/power_stat.cc | 467 +++++++++++++++++++++++++------------------- 1 file changed, 268 insertions(+), 199 deletions(-) (limited to 'src/gpgpu-sim/power_stat.cc') diff --git a/src/gpgpu-sim/power_stat.cc b/src/gpgpu-sim/power_stat.cc index 7b60ddf..fd7a775 100644 --- a/src/gpgpu-sim/power_stat.cc +++ b/src/gpgpu-sim/power_stat.cc @@ -1,18 +1,19 @@ -// Copyright (c) 2009-2011, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington -// The University of British Columbia +// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas +// The University of British Columbia, Northwestern University // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. Neither the name of -// The University of British Columbia nor the names of its contributors may be -// used to endorse or promote products derived from this software without -// specific prior written permission. +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer; +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution; +// 3. Neither the names of The University of British Columbia, Northwestern +// University nor the names of their contributors may be used to +// endorse or promote products derived from this software without specific +// prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -54,10 +55,64 @@ power_mem_stat_t::power_mem_stat_t(const memory_config *mem_config, init(); } +void power_stat_t::clear(){ + for(unsigned i=0; i< NUM_STAT_IDX; ++i){ + pwr_mem_stat->core_cache_stats[i].clear(); + pwr_mem_stat->l2_cache_stats[i].clear(); + for(unsigned j=0; jnum_shader(); ++j){ + pwr_core_stat->m_pipeline_duty_cycle[i][j]=0; + pwr_core_stat->m_num_decoded_insn[i][j]=0; + pwr_core_stat->m_num_FPdecoded_insn[i][j]=0; + pwr_core_stat->m_num_INTdecoded_insn[i][j]=0; + pwr_core_stat->m_num_storequeued_insn[i][j]=0; + pwr_core_stat->m_num_loadqueued_insn[i][j]=0; + pwr_core_stat->m_num_tex_inst[i][j]=0; + pwr_core_stat->m_num_ialu_acesses[i][j]=0; + pwr_core_stat->m_num_fp_acesses[i][j]=0; + pwr_core_stat->m_num_imul_acesses[i][j]=0; + pwr_core_stat->m_num_imul24_acesses[i][j]=0; + pwr_core_stat->m_num_imul32_acesses[i][j]=0; + pwr_core_stat->m_num_fpmul_acesses[i][j]=0; + pwr_core_stat->m_num_idiv_acesses[i][j]=0; + pwr_core_stat->m_num_fpdiv_acesses[i][j]=0; + pwr_core_stat->m_num_dp_acesses[i][j]=0; + pwr_core_stat->m_num_dpmul_acesses[i][j]=0; + pwr_core_stat->m_num_dpdiv_acesses[i][j]=0; + pwr_core_stat->m_num_tensor_core_acesses[i][j]=0; + pwr_core_stat->m_num_const_acesses[i][j]=0; + pwr_core_stat->m_num_tex_acesses[i][j]=0; + pwr_core_stat->m_num_sp_acesses[i][j]=0; + pwr_core_stat->m_num_sfu_acesses[i][j]=0; + pwr_core_stat->m_num_sqrt_acesses[i][j]=0; + pwr_core_stat->m_num_log_acesses[i][j]=0; + pwr_core_stat->m_num_sin_acesses[i][j]=0; + pwr_core_stat->m_num_exp_acesses[i][j]=0; + pwr_core_stat->m_num_mem_acesses[i][j]=0; + pwr_core_stat->m_num_sp_committed[i][j]=0; + pwr_core_stat->m_num_sfu_committed[i][j]=0; + pwr_core_stat->m_num_mem_committed[i][j]=0; + pwr_core_stat->m_read_regfile_acesses[i][j]=0; + pwr_core_stat->m_write_regfile_acesses[i][j]=0; + pwr_core_stat->m_non_rf_operands[i][j]=0; + pwr_core_stat->m_active_sp_lanes[i][j]=0; + pwr_core_stat->m_active_sfu_lanes[i][j]=0; + pwr_core_stat->m_active_exu_threads[i][j]=0; + pwr_core_stat->m_active_exu_warps[i][j]=0; + } + for (unsigned j = 0; j < m_mem_config->m_n_mem; ++j) { + pwr_mem_stat->n_rd[i][j]=0; + pwr_mem_stat->n_wr[i][j]=0; + pwr_mem_stat->n_pre[i][j]=0; + } + } +} + + + void power_mem_stat_t::init() { - shmem_read_access[CURRENT_STAT_IDX] = + shmem_access[CURRENT_STAT_IDX] = m_core_stats->gpgpu_n_shmem_bank_access; // Shared memory access - shmem_read_access[PREV_STAT_IDX] = + shmem_access[PREV_STAT_IDX] = (unsigned *)calloc(m_core_config->num_shader(), sizeof(unsigned)); for (unsigned i = 0; i < NUM_STAT_IDX; ++i) { @@ -71,6 +126,7 @@ void power_mem_stat_t::init() { n_pre[i] = (unsigned *)calloc(m_config->m_n_mem, sizeof(unsigned)); n_rd[i] = (unsigned *)calloc(m_config->m_n_mem, sizeof(unsigned)); n_wr[i] = (unsigned *)calloc(m_config->m_n_mem, sizeof(unsigned)); + n_wr_WB[i] = (unsigned *)calloc(m_config->m_n_mem, sizeof(unsigned)); n_req[i] = (unsigned *)calloc(m_config->m_n_mem, sizeof(unsigned)); // Interconnect stats @@ -86,8 +142,8 @@ void power_mem_stat_t::save_stats() { l2_cache_stats[PREV_STAT_IDX] = l2_cache_stats[CURRENT_STAT_IDX]; for (unsigned i = 0; i < m_core_config->num_shader(); ++i) { - shmem_read_access[PREV_STAT_IDX][i] = - shmem_read_access[CURRENT_STAT_IDX][i]; // Shared memory access + shmem_access[PREV_STAT_IDX][i] = + shmem_access[CURRENT_STAT_IDX][i]; // Shared memory access } for (unsigned i = 0; i < m_config->m_n_mem; ++i) { @@ -98,6 +154,7 @@ void power_mem_stat_t::save_stats() { n_pre[PREV_STAT_IDX][i] = n_pre[CURRENT_STAT_IDX][i]; n_rd[PREV_STAT_IDX][i] = n_rd[CURRENT_STAT_IDX][i]; n_wr[PREV_STAT_IDX][i] = n_wr[CURRENT_STAT_IDX][i]; + n_wr_WB[PREV_STAT_IDX][i] = n_wr_WB[CURRENT_STAT_IDX][i]; n_req[PREV_STAT_IDX][i] = n_req[CURRENT_STAT_IDX][i]; } @@ -117,7 +174,7 @@ void power_mem_stat_t::print(FILE *fout) const { unsigned total_mem_writes = 0; for (unsigned i = 0; i < m_config->m_n_mem; ++i) { total_mem_reads += n_rd[CURRENT_STAT_IDX][i]; - total_mem_writes += n_wr[CURRENT_STAT_IDX][i]; + total_mem_writes += n_wr[CURRENT_STAT_IDX][i] + n_wr_WB[CURRENT_STAT_IDX][i]; } fprintf(fout, "Total memory controller accesses: %u\n", total_mem_reads + total_mem_writes); @@ -147,198 +204,165 @@ void power_core_stat_t::print(FILE *fout) { // per core statistics fprintf(fout, "Power Metrics: \n"); for (unsigned i = 0; i < m_config->num_shader(); i++) { - fprintf(fout, "core %u:\n", i); - fprintf(fout, "\tpipeline duty cycle =%f\n", - m_pipeline_duty_cycle[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal Deocded Instructions=%u\n", - m_num_decoded_insn[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal FP Deocded Instructions=%u\n", - m_num_FPdecoded_insn[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal INT Deocded Instructions=%u\n", - m_num_INTdecoded_insn[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal LOAD Queued Instructions=%u\n", - m_num_loadqueued_insn[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal STORE Queued Instructions=%u\n", - m_num_storequeued_insn[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal IALU Acesses=%u\n", - m_num_ialu_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal FP Acesses=%u\n", - m_num_fp_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal IMUL Acesses=%u\n", - m_num_imul_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal IMUL24 Acesses=%u\n", - m_num_imul24_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal IMUL32 Acesses=%u\n", - m_num_imul32_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal IDIV Acesses=%u\n", - m_num_idiv_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal FPMUL Acesses=%u\n", - m_num_fpmul_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal SFU Acesses=%u\n", - m_num_trans_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal FPDIV Acesses=%u\n", - m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal SFU Acesses=%u\n", - m_num_sfu_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal SP Acesses=%u\n", - m_num_sp_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal MEM Acesses=%u\n", - m_num_mem_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal SFU Commissions=%u\n", - m_num_sfu_committed[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal SP Commissions=%u\n", - m_num_sp_committed[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal MEM Commissions=%u\n", - m_num_mem_committed[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal REG Reads=%u\n", - m_read_regfile_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal REG Writes=%u\n", - m_write_regfile_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout, "\tTotal NON REG=%u\n", - m_non_rf_operands[CURRENT_STAT_IDX][i]); + fprintf(fout,"core %u:\n",i); + fprintf(fout,"\tpipeline duty cycle =%f\n",m_pipeline_duty_cycle[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal Deocded Instructions=%u\n",m_num_decoded_insn[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal FP Deocded Instructions=%u\n",m_num_FPdecoded_insn[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal INT Deocded Instructions=%u\n",m_num_INTdecoded_insn[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal LOAD Queued Instructions=%u\n",m_num_loadqueued_insn[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal STORE Queued Instructions=%u\n",m_num_storequeued_insn[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal IALU Acesses=%f\n",m_num_ialu_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal FP Acesses=%f\n",m_num_fp_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal DP Acesses=%f\n",m_num_dp_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal IMUL Acesses=%f\n",m_num_imul_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal IMUL24 Acesses=%f\n",m_num_imul24_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal IMUL32 Acesses=%f\n",m_num_imul32_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal IDIV Acesses=%f\n",m_num_idiv_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal FPMUL Acesses=%f\n",m_num_fpmul_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal DPMUL Acesses=%f\n",m_num_dpmul_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal SQRT Acesses=%f\n",m_num_sqrt_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal LOG Acesses=%f\n",m_num_log_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal SIN Acesses=%f\n",m_num_sin_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal EXP Acesses=%f\n",m_num_exp_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal FPDIV Acesses=%f\n",m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal DPDIV Acesses=%f\n",m_num_dpdiv_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal TENSOR Acesses=%f\n",m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal CONST Acesses=%f\n",m_num_const_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal TEX Acesses=%f\n",m_num_tex_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal SFU Acesses=%f\n",m_num_sfu_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal SP Acesses=%f\n",m_num_sp_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal MEM Acesses=%f\n",m_num_mem_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal SFU Commissions=%u\n",m_num_sfu_committed[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal SP Commissions=%u\n",m_num_sp_committed[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal MEM Commissions=%u\n",m_num_mem_committed[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal REG Reads=%u\n",m_read_regfile_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal REG Writes=%u\n",m_write_regfile_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout,"\tTotal NON REG=%u\n",m_non_rf_operands[CURRENT_STAT_IDX][i]); } } void power_core_stat_t::init() { - m_pipeline_duty_cycle[CURRENT_STAT_IDX] = m_core_stats->m_pipeline_duty_cycle; - m_num_decoded_insn[CURRENT_STAT_IDX] = m_core_stats->m_num_decoded_insn; - m_num_FPdecoded_insn[CURRENT_STAT_IDX] = m_core_stats->m_num_FPdecoded_insn; - m_num_INTdecoded_insn[CURRENT_STAT_IDX] = m_core_stats->m_num_INTdecoded_insn; - m_num_storequeued_insn[CURRENT_STAT_IDX] = - m_core_stats->m_num_storequeued_insn; - m_num_loadqueued_insn[CURRENT_STAT_IDX] = m_core_stats->m_num_loadqueued_insn; - m_num_ialu_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_ialu_acesses; - m_num_fp_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_fp_acesses; - m_num_imul_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_imul_acesses; - m_num_imul24_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_imul24_acesses; - m_num_imul32_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_imul32_acesses; - m_num_fpmul_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_fpmul_acesses; - m_num_idiv_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_idiv_acesses; - m_num_fpdiv_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_fpdiv_acesses; - m_num_sp_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_sp_acesses; - m_num_sfu_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_sfu_acesses; - m_num_trans_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_trans_acesses; - m_num_mem_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_mem_acesses; - m_num_sp_committed[CURRENT_STAT_IDX] = m_core_stats->m_num_sp_committed; - m_num_sfu_committed[CURRENT_STAT_IDX] = m_core_stats->m_num_sfu_committed; - m_num_mem_committed[CURRENT_STAT_IDX] = m_core_stats->m_num_mem_committed; - m_read_regfile_acesses[CURRENT_STAT_IDX] = - m_core_stats->m_read_regfile_acesses; - m_write_regfile_acesses[CURRENT_STAT_IDX] = - m_core_stats->m_write_regfile_acesses; - m_non_rf_operands[CURRENT_STAT_IDX] = m_core_stats->m_non_rf_operands; - m_active_sp_lanes[CURRENT_STAT_IDX] = m_core_stats->m_active_sp_lanes; - m_active_sfu_lanes[CURRENT_STAT_IDX] = m_core_stats->m_active_sfu_lanes; - m_num_tex_inst[CURRENT_STAT_IDX] = m_core_stats->m_num_tex_inst; + m_pipeline_duty_cycle[CURRENT_STAT_IDX]=m_core_stats->m_pipeline_duty_cycle; + m_num_decoded_insn[CURRENT_STAT_IDX]=m_core_stats->m_num_decoded_insn; + m_num_FPdecoded_insn[CURRENT_STAT_IDX]=m_core_stats->m_num_FPdecoded_insn; + m_num_INTdecoded_insn[CURRENT_STAT_IDX]=m_core_stats->m_num_INTdecoded_insn; + m_num_storequeued_insn[CURRENT_STAT_IDX]=m_core_stats->m_num_storequeued_insn; + m_num_loadqueued_insn[CURRENT_STAT_IDX]=m_core_stats->m_num_loadqueued_insn; + m_num_ialu_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_ialu_acesses; + m_num_fp_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_fp_acesses; + m_num_imul_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_imul_acesses; + m_num_imul24_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_imul24_acesses; + m_num_imul32_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_imul32_acesses; + m_num_fpmul_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_fpmul_acesses; + m_num_idiv_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_idiv_acesses; + m_num_fpdiv_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_fpdiv_acesses; + m_num_dp_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_dp_acesses; + m_num_dpmul_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_dpmul_acesses; + m_num_dpdiv_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_dpdiv_acesses; + m_num_sp_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_sp_acesses; + m_num_sfu_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_sfu_acesses; + m_num_sqrt_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_sqrt_acesses; + m_num_log_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_log_acesses; + m_num_sin_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_sin_acesses; + m_num_exp_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_exp_acesses; + m_num_tensor_core_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_tensor_core_acesses; + m_num_const_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_const_acesses; + m_num_tex_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_tex_acesses; + m_num_mem_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_mem_acesses; + m_num_sp_committed[CURRENT_STAT_IDX]=m_core_stats->m_num_sp_committed; + m_num_sfu_committed[CURRENT_STAT_IDX]=m_core_stats->m_num_sfu_committed; + m_num_mem_committed[CURRENT_STAT_IDX]=m_core_stats->m_num_mem_committed; + m_read_regfile_acesses[CURRENT_STAT_IDX]=m_core_stats->m_read_regfile_acesses; + m_write_regfile_acesses[CURRENT_STAT_IDX]=m_core_stats->m_write_regfile_acesses; + m_non_rf_operands[CURRENT_STAT_IDX]=m_core_stats->m_non_rf_operands; + m_active_sp_lanes[CURRENT_STAT_IDX]=m_core_stats->m_active_sp_lanes; + m_active_sfu_lanes[CURRENT_STAT_IDX]=m_core_stats->m_active_sfu_lanes; + m_active_exu_threads[CURRENT_STAT_IDX]=m_core_stats->m_active_exu_threads; + m_active_exu_warps[CURRENT_STAT_IDX]=m_core_stats->m_active_exu_warps; + m_num_tex_inst[CURRENT_STAT_IDX]=m_core_stats->m_num_tex_inst; + + m_pipeline_duty_cycle[PREV_STAT_IDX]=(float*)calloc(m_config->num_shader(),sizeof(float)); + m_num_decoded_insn[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); + m_num_FPdecoded_insn[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); + m_num_INTdecoded_insn[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); + m_num_storequeued_insn[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); + m_num_loadqueued_insn[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); + m_num_tex_inst[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); + + m_num_ialu_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_fp_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_imul_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_imul24_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_imul32_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_fpmul_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_idiv_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_fpdiv_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_dp_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_dpmul_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_dpdiv_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_tensor_core_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_const_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_tex_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_sp_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_sfu_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_sqrt_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_log_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_sin_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_exp_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_mem_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_num_sp_committed[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); + m_num_sfu_committed[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); + m_num_mem_committed[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); + m_read_regfile_acesses[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); + m_write_regfile_acesses[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); + m_non_rf_operands[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); + m_active_sp_lanes[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); + m_active_sfu_lanes[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); + m_active_exu_threads[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_active_exu_warps[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + - m_pipeline_duty_cycle[PREV_STAT_IDX] = - (float *)calloc(m_config->num_shader(), sizeof(float)); - m_num_decoded_insn[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_FPdecoded_insn[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_INTdecoded_insn[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_storequeued_insn[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_loadqueued_insn[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_ialu_acesses[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_fp_acesses[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_tex_inst[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_imul_acesses[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_imul24_acesses[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_imul32_acesses[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_fpmul_acesses[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_idiv_acesses[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_fpdiv_acesses[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_sp_acesses[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_sfu_acesses[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_trans_acesses[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_mem_acesses[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_sp_committed[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_sfu_committed[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_num_mem_committed[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_read_regfile_acesses[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_write_regfile_acesses[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_non_rf_operands[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_active_sp_lanes[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); - m_active_sfu_lanes[PREV_STAT_IDX] = - (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); } void power_core_stat_t::save_stats() { for (unsigned i = 0; i < m_config->num_shader(); ++i) { - m_pipeline_duty_cycle[PREV_STAT_IDX][i] = - m_pipeline_duty_cycle[CURRENT_STAT_IDX][i]; - m_num_decoded_insn[PREV_STAT_IDX][i] = - m_num_decoded_insn[CURRENT_STAT_IDX][i]; - m_num_FPdecoded_insn[PREV_STAT_IDX][i] = - m_num_FPdecoded_insn[CURRENT_STAT_IDX][i]; - m_num_INTdecoded_insn[PREV_STAT_IDX][i] = - m_num_INTdecoded_insn[CURRENT_STAT_IDX][i]; - m_num_storequeued_insn[PREV_STAT_IDX][i] = - m_num_storequeued_insn[CURRENT_STAT_IDX][i]; - m_num_loadqueued_insn[PREV_STAT_IDX][i] = - m_num_loadqueued_insn[CURRENT_STAT_IDX][i]; - m_num_ialu_acesses[PREV_STAT_IDX][i] = - m_num_ialu_acesses[CURRENT_STAT_IDX][i]; - m_num_fp_acesses[PREV_STAT_IDX][i] = m_num_fp_acesses[CURRENT_STAT_IDX][i]; - m_num_tex_inst[PREV_STAT_IDX][i] = m_num_tex_inst[CURRENT_STAT_IDX][i]; - m_num_imul_acesses[PREV_STAT_IDX][i] = - m_num_imul_acesses[CURRENT_STAT_IDX][i]; - m_num_imul24_acesses[PREV_STAT_IDX][i] = - m_num_imul24_acesses[CURRENT_STAT_IDX][i]; - m_num_imul32_acesses[PREV_STAT_IDX][i] = - m_num_imul32_acesses[CURRENT_STAT_IDX][i]; - m_num_fpmul_acesses[PREV_STAT_IDX][i] = - m_num_fpmul_acesses[CURRENT_STAT_IDX][i]; - m_num_idiv_acesses[PREV_STAT_IDX][i] = - m_num_idiv_acesses[CURRENT_STAT_IDX][i]; - m_num_fpdiv_acesses[PREV_STAT_IDX][i] = - m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]; - m_num_sp_acesses[PREV_STAT_IDX][i] = m_num_sp_acesses[CURRENT_STAT_IDX][i]; - m_num_sfu_acesses[PREV_STAT_IDX][i] = - m_num_sfu_acesses[CURRENT_STAT_IDX][i]; - m_num_trans_acesses[PREV_STAT_IDX][i] = - m_num_trans_acesses[CURRENT_STAT_IDX][i]; - m_num_mem_acesses[PREV_STAT_IDX][i] = - m_num_mem_acesses[CURRENT_STAT_IDX][i]; - m_num_sp_committed[PREV_STAT_IDX][i] = - m_num_sp_committed[CURRENT_STAT_IDX][i]; - m_num_sfu_committed[PREV_STAT_IDX][i] = - m_num_sfu_committed[CURRENT_STAT_IDX][i]; - m_num_mem_committed[PREV_STAT_IDX][i] = - m_num_mem_committed[CURRENT_STAT_IDX][i]; - m_read_regfile_acesses[PREV_STAT_IDX][i] = - m_read_regfile_acesses[CURRENT_STAT_IDX][i]; - m_write_regfile_acesses[PREV_STAT_IDX][i] = - m_write_regfile_acesses[CURRENT_STAT_IDX][i]; - m_non_rf_operands[PREV_STAT_IDX][i] = - m_non_rf_operands[CURRENT_STAT_IDX][i]; - m_active_sp_lanes[PREV_STAT_IDX][i] = - m_active_sp_lanes[CURRENT_STAT_IDX][i]; - m_active_sfu_lanes[PREV_STAT_IDX][i] = - m_active_sfu_lanes[CURRENT_STAT_IDX][i]; + m_pipeline_duty_cycle[PREV_STAT_IDX][i]=m_pipeline_duty_cycle[CURRENT_STAT_IDX][i]; + m_num_decoded_insn[PREV_STAT_IDX][i]= m_num_decoded_insn[CURRENT_STAT_IDX][i]; + m_num_FPdecoded_insn[PREV_STAT_IDX][i]=m_num_FPdecoded_insn[CURRENT_STAT_IDX][i]; + m_num_INTdecoded_insn[PREV_STAT_IDX][i]=m_num_INTdecoded_insn[CURRENT_STAT_IDX][i]; + m_num_storequeued_insn[PREV_STAT_IDX][i]=m_num_storequeued_insn[CURRENT_STAT_IDX][i]; + m_num_loadqueued_insn[PREV_STAT_IDX][i]=m_num_loadqueued_insn[CURRENT_STAT_IDX][i]; + m_num_ialu_acesses[PREV_STAT_IDX][i]=m_num_ialu_acesses[CURRENT_STAT_IDX][i]; + m_num_fp_acesses[PREV_STAT_IDX][i]=m_num_fp_acesses[CURRENT_STAT_IDX][i]; + m_num_tex_inst[PREV_STAT_IDX][i]=m_num_tex_inst[CURRENT_STAT_IDX][i]; + m_num_imul_acesses[PREV_STAT_IDX][i]=m_num_imul_acesses[CURRENT_STAT_IDX][i]; + m_num_imul24_acesses[PREV_STAT_IDX][i]=m_num_imul24_acesses[CURRENT_STAT_IDX][i]; + m_num_imul32_acesses[PREV_STAT_IDX][i]=m_num_imul32_acesses[CURRENT_STAT_IDX][i]; + m_num_fpmul_acesses[PREV_STAT_IDX][i]=m_num_fpmul_acesses[CURRENT_STAT_IDX][i]; + m_num_idiv_acesses[PREV_STAT_IDX][i]=m_num_idiv_acesses[CURRENT_STAT_IDX][i]; + m_num_fpdiv_acesses[PREV_STAT_IDX][i]=m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]; + m_num_sp_acesses[PREV_STAT_IDX][i]=m_num_sp_acesses[CURRENT_STAT_IDX][i]; + m_num_sfu_acesses[PREV_STAT_IDX][i]=m_num_sfu_acesses[CURRENT_STAT_IDX][i]; + m_num_sqrt_acesses[PREV_STAT_IDX][i]=m_num_sqrt_acesses[CURRENT_STAT_IDX][i]; + m_num_log_acesses[PREV_STAT_IDX][i]=m_num_log_acesses[CURRENT_STAT_IDX][i]; + m_num_sin_acesses[PREV_STAT_IDX][i]=m_num_sin_acesses[CURRENT_STAT_IDX][i]; + m_num_exp_acesses[PREV_STAT_IDX][i]=m_num_exp_acesses[CURRENT_STAT_IDX][i]; + m_num_dp_acesses[PREV_STAT_IDX][i]=m_num_dp_acesses[CURRENT_STAT_IDX][i]; + m_num_dpmul_acesses[PREV_STAT_IDX][i]=m_num_dpmul_acesses[CURRENT_STAT_IDX][i]; + m_num_dpdiv_acesses[PREV_STAT_IDX][i]=m_num_dpdiv_acesses[CURRENT_STAT_IDX][i]; + m_num_tensor_core_acesses[PREV_STAT_IDX][i]=m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]; + m_num_const_acesses[PREV_STAT_IDX][i]=m_num_const_acesses[CURRENT_STAT_IDX][i]; + m_num_tex_acesses[PREV_STAT_IDX][i]=m_num_tex_acesses[CURRENT_STAT_IDX][i]; + m_num_mem_acesses[PREV_STAT_IDX][i]=m_num_mem_acesses[CURRENT_STAT_IDX][i]; + m_num_sp_committed[PREV_STAT_IDX][i]=m_num_sp_committed[CURRENT_STAT_IDX][i]; + m_num_sfu_committed[PREV_STAT_IDX][i]=m_num_sfu_committed[CURRENT_STAT_IDX][i]; + m_num_mem_committed[PREV_STAT_IDX][i]=m_num_mem_committed[CURRENT_STAT_IDX][i]; + m_read_regfile_acesses[PREV_STAT_IDX][i]=m_read_regfile_acesses[CURRENT_STAT_IDX][i]; + m_write_regfile_acesses[PREV_STAT_IDX][i]=m_write_regfile_acesses[CURRENT_STAT_IDX][i]; + m_non_rf_operands[PREV_STAT_IDX][i]=m_non_rf_operands[CURRENT_STAT_IDX][i]; + m_active_sp_lanes[PREV_STAT_IDX][i]=m_active_sp_lanes[CURRENT_STAT_IDX][i]; + m_active_sfu_lanes[PREV_STAT_IDX][i]=m_active_sfu_lanes[CURRENT_STAT_IDX][i]; + m_active_exu_threads[PREV_STAT_IDX][i]=m_active_exu_threads[CURRENT_STAT_IDX][i]; + m_active_exu_warps[PREV_STAT_IDX][i]=m_active_exu_warps[CURRENT_STAT_IDX][i]; } } @@ -356,6 +380,51 @@ power_stat_t::power_stat_t(const shader_core_config *shader_config, m_active_sms = active_sms; m_config = shader_config; m_mem_config = mem_config; + l1r_hits_kernel = 0; + l1r_misses_kernel = 0; + l1w_hits_kernel = 0; + l1w_misses_kernel = 0; + shared_accesses_kernel = 0; + cc_accesses_kernel = 0; + dram_rd_kernel = 0; + dram_wr_kernel = 0; + dram_pre_kernel = 0; + l1i_hits_kernel =0; + l1i_misses_kernel =0; + l2r_hits_kernel =0; + l2r_misses_kernel =0; + l2w_hits_kernel =0; + l2w_misses_kernel =0; + noc_tr_kernel = 0; + noc_rc_kernel = 0; + + tot_inst_execution = 0; + tot_int_inst_execution = 0; + tot_fp_inst_execution = 0; + commited_inst_execution = 0; + ialu_acc_execution = 0; + imul24_acc_execution = 0; + imul32_acc_execution = 0; + imul_acc_execution = 0; + idiv_acc_execution = 0; + dp_acc_execution = 0; + dpmul_acc_execution = 0; + dpdiv_acc_execution = 0; + fp_acc_execution = 0; + fpmul_acc_execution = 0; + fpdiv_acc_execution = 0; + sqrt_acc_execution = 0; + log_acc_execution = 0; + sin_acc_execution = 0; + exp_acc_execution = 0; + tensor_acc_execution = 0; + tex_acc_execution = 0; + tot_fpu_acc_execution = 0; + tot_sfu_acc_execution = 0; + tot_threads_acc_execution = 0; + tot_warps_acc_execution = 0; + sp_active_lanes_execution = 0; + sfu_active_lanes_execution = 0; } void power_stat_t::visualizer_print(gzFile visualizer_file) { -- cgit v1.3 From 011891abfae060903f76d5c7aee23208cd295e71 Mon Sep 17 00:00:00 2001 From: JRPAN <25518778+JRPan@users.noreply.github.com> Date: Tue, 1 Feb 2022 20:36:24 -0500 Subject: Update Copyrights --- src/abstract_hardware_model.cc | 5 +++-- src/abstract_hardware_model.h | 5 +++-- src/cuda-sim/cuda-sim.cc | 5 +++-- src/cuda-sim/instructions.cc | 5 +++-- src/cuda-sim/ptx.l | 5 +++-- src/cuda-sim/ptx_ir.cc | 5 +++-- src/gpgpu-sim/dram.cc | 5 +++-- src/gpgpu-sim/dram.h | 5 +++-- src/gpgpu-sim/gpu-cache.cc | 6 ++++-- src/gpgpu-sim/gpu-cache.h | 5 +++-- src/gpgpu-sim/gpu-sim.cc | 5 +++-- src/gpgpu-sim/gpu-sim.h | 3 ++- src/gpgpu-sim/l2cache.cc | 5 +++-- src/gpgpu-sim/l2cache.h | 5 +++-- src/gpgpu-sim/power_interface.cc | 5 +++-- src/gpgpu-sim/power_interface.h | 5 +++-- src/gpgpu-sim/power_stat.cc | 5 +++-- src/gpgpu-sim/power_stat.h | 5 +++-- src/gpgpu-sim/shader.cc | 5 +++-- src/gpgpu-sim/shader.h | 5 +++-- 20 files changed, 60 insertions(+), 39 deletions(-) (limited to 'src/gpgpu-sim/power_stat.cc') diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index 208047e..fda84e8 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Inderpreet Singh, Timothy Rogers, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Inderpreet Singh, Timothy Rogers, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index f04741f..e9d7c76 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Inderpreet Singh, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Inderpreet Singh, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index f9e5db3..680ce79 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Ali Bakhoda, Wilson W.L. Fung, -// George L. Yuan, Jimmy Kwa, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// George L. Yuan, Jimmy Kwa, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 44afbe5..e22d88a 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda, -// Jimmy Kwa, George L. Yuan, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Jimmy Kwa, George L. Yuan, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 7706f0b..15b3cf7 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -1,6 +1,7 @@ /* -Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas -The University of British Columbia, Northwestern University +Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas, +Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +The University of British Columbia, Northwestern University, Purdue University All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 2edc1ed..029cf73 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Ali Bakhoda, Wilson W.L. Fung, -// George L. Yuan, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// George L. Yuan, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index 545c45d..662c2ed 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda, -// Ivan Sham, George L. Yuan, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Ivan Sham, George L. Yuan, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index 88e46ed..90ea3e4 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Ivan Sham, Ali Bakhoda, -// George L. Yuan, Wilson W.L. Fung, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// George L. Yuan, Wilson W.L. Fung, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index a2aeec5..3a5a67d 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -1,5 +1,7 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, +// Vijay Kandiah, Nikos Hardavellas, Mahmoud Khairy, Junrui Pan, +// Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 498dfeb..4bbf7e2 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index e44551e..ee243c1 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, George L. Yuan, -// Ali Bakhoda, Andrew Turner, Ivan Sham, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Ali Bakhoda, Andrew Turner, Ivan Sham, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 68b3dfa..de69ef8 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -1,5 +1,6 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index 511c15e..44d793c 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index 902a4b7..7fa1f29 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/power_interface.cc b/src/gpgpu-sim/power_interface.cc index 63b9852..470f2f9 100644 --- a/src/gpgpu-sim/power_interface.cc +++ b/src/gpgpu-sim/power_interface.cc @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/power_interface.h b/src/gpgpu-sim/power_interface.h index 1a48894..1c6c510 100644 --- a/src/gpgpu-sim/power_interface.h +++ b/src/gpgpu-sim/power_interface.h @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/power_stat.cc b/src/gpgpu-sim/power_stat.cc index fd7a775..d0e673c 100644 --- a/src/gpgpu-sim/power_stat.cc +++ b/src/gpgpu-sim/power_stat.cc @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/power_stat.h b/src/gpgpu-sim/power_stat.h index e2c3ed5..d40f1d9 100644 --- a/src/gpgpu-sim/power_stat.h +++ b/src/gpgpu-sim/power_stat.h @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index c0161dd..9f8a129 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda, -// George L. Yuan, Andrew Turner, Inderpreet Singh, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// George L. Yuan, Andrew Turner, Inderpreet Singh, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 65d5625..d80476f 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Andrew Turner, -// Ali Bakhoda, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Ali Bakhoda, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without -- cgit v1.3