From 84c6cf45131e42b1a724ebf7977987a9ddb70db9 Mon Sep 17 00:00:00 2001 From: VijayKandiah Date: Sun, 17 Oct 2021 02:18:10 -0500 Subject: AccelWattch dev Integration --- src/gpgpu-sim/power_stat.h | 832 +++++++++++++++++++++++++++++++++------------ 1 file changed, 615 insertions(+), 217 deletions(-) (limited to 'src/gpgpu-sim/power_stat.h') diff --git a/src/gpgpu-sim/power_stat.h b/src/gpgpu-sim/power_stat.h index c469db3..e2c3ed5 100644 --- a/src/gpgpu-sim/power_stat.h +++ b/src/gpgpu-sim/power_stat.h @@ -1,18 +1,19 @@ -// Copyright (c) 2009-2011, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington -// The University of British Columbia +// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas +// The University of British Columbia, Northwestern University // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. Neither the name of -// The University of British Columbia nor the names of its contributors may be -// used to endorse or promote products derived from this software without -// specific prior written permission. +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer; +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution; +// 3. Neither the names of The University of British Columbia, Northwestern +// University nor the names of their contributors may be used to +// endorse or promote products derived from this software without specific +// prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -51,29 +52,40 @@ struct shader_core_power_stats_pod { unsigned *m_num_INTdecoded_insn[NUM_STAT_IDX]; // number of instructions committed // by this shader core - unsigned *m_num_storequeued_insn[NUM_STAT_IDX]; - unsigned *m_num_loadqueued_insn[NUM_STAT_IDX]; - unsigned *m_num_ialu_acesses[NUM_STAT_IDX]; - unsigned *m_num_fp_acesses[NUM_STAT_IDX]; - unsigned *m_num_tex_inst[NUM_STAT_IDX]; - unsigned *m_num_imul_acesses[NUM_STAT_IDX]; - unsigned *m_num_imul32_acesses[NUM_STAT_IDX]; - unsigned *m_num_imul24_acesses[NUM_STAT_IDX]; - unsigned *m_num_fpmul_acesses[NUM_STAT_IDX]; - unsigned *m_num_idiv_acesses[NUM_STAT_IDX]; - unsigned *m_num_fpdiv_acesses[NUM_STAT_IDX]; - unsigned *m_num_sp_acesses[NUM_STAT_IDX]; - unsigned *m_num_sfu_acesses[NUM_STAT_IDX]; - unsigned *m_num_trans_acesses[NUM_STAT_IDX]; - unsigned *m_num_mem_acesses[NUM_STAT_IDX]; - unsigned *m_num_sp_committed[NUM_STAT_IDX]; - unsigned *m_num_sfu_committed[NUM_STAT_IDX]; - unsigned *m_num_mem_committed[NUM_STAT_IDX]; - unsigned *m_active_sp_lanes[NUM_STAT_IDX]; - unsigned *m_active_sfu_lanes[NUM_STAT_IDX]; - unsigned *m_read_regfile_acesses[NUM_STAT_IDX]; - unsigned *m_write_regfile_acesses[NUM_STAT_IDX]; - unsigned *m_non_rf_operands[NUM_STAT_IDX]; + unsigned *m_num_storequeued_insn[NUM_STAT_IDX]; + unsigned *m_num_loadqueued_insn[NUM_STAT_IDX]; + unsigned *m_num_tex_inst[NUM_STAT_IDX]; + double *m_num_ialu_acesses[NUM_STAT_IDX]; + double *m_num_fp_acesses[NUM_STAT_IDX]; + double *m_num_imul_acesses[NUM_STAT_IDX]; + double *m_num_imul32_acesses[NUM_STAT_IDX]; + double *m_num_imul24_acesses[NUM_STAT_IDX]; + double *m_num_fpmul_acesses[NUM_STAT_IDX]; + double *m_num_idiv_acesses[NUM_STAT_IDX]; + double *m_num_fpdiv_acesses[NUM_STAT_IDX]; + double *m_num_dp_acesses[NUM_STAT_IDX]; + double *m_num_dpmul_acesses[NUM_STAT_IDX]; + double *m_num_dpdiv_acesses[NUM_STAT_IDX]; + double *m_num_sp_acesses[NUM_STAT_IDX]; + double *m_num_sfu_acesses[NUM_STAT_IDX]; + double *m_num_sqrt_acesses[NUM_STAT_IDX]; + double *m_num_log_acesses[NUM_STAT_IDX]; + double *m_num_sin_acesses[NUM_STAT_IDX]; + double *m_num_exp_acesses[NUM_STAT_IDX]; + double *m_num_tensor_core_acesses[NUM_STAT_IDX]; + double *m_num_const_acesses[NUM_STAT_IDX]; + double *m_num_tex_acesses[NUM_STAT_IDX]; + double *m_num_mem_acesses[NUM_STAT_IDX]; + unsigned *m_num_sp_committed[NUM_STAT_IDX]; + unsigned *m_num_sfu_committed[NUM_STAT_IDX]; + unsigned *m_num_mem_committed[NUM_STAT_IDX]; + unsigned *m_active_sp_lanes[NUM_STAT_IDX]; + unsigned *m_active_sfu_lanes[NUM_STAT_IDX]; + double *m_active_exu_threads[NUM_STAT_IDX]; + double *m_active_exu_warps[NUM_STAT_IDX]; + unsigned *m_read_regfile_acesses[NUM_STAT_IDX]; + unsigned *m_write_regfile_acesses[NUM_STAT_IDX]; + unsigned *m_non_rf_operands[NUM_STAT_IDX]; }; class power_core_stat_t : public shader_core_power_stats_pod { @@ -84,6 +96,7 @@ class power_core_stat_t : public shader_core_power_stats_pod { void print(FILE *fout); void init(); void save_stats(); + private: shader_core_stats *m_core_stats; @@ -96,8 +109,7 @@ struct mem_power_stats_pod { class cache_stats core_cache_stats[NUM_STAT_IDX]; // Total core stats class cache_stats l2_cache_stats[NUM_STAT_IDX]; // Total L2 partition stats - unsigned *shmem_read_access[NUM_STAT_IDX]; // Shared memory access - + unsigned *shmem_access[NUM_STAT_IDX]; // Shared memory access // Low level DRAM stats unsigned *n_cmd[NUM_STAT_IDX]; unsigned *n_activity[NUM_STAT_IDX]; @@ -106,6 +118,7 @@ struct mem_power_stats_pod { unsigned *n_pre[NUM_STAT_IDX]; unsigned *n_rd[NUM_STAT_IDX]; unsigned *n_wr[NUM_STAT_IDX]; + unsigned *n_wr_WB[NUM_STAT_IDX]; unsigned *n_req[NUM_STAT_IDX]; // Interconnect stats @@ -144,34 +157,88 @@ class power_stat_t { *m_average_pipeline_duty_cycle = 0; *m_active_sms = 0; } - - unsigned get_total_inst() { - unsigned total_inst = 0; + void clear(); + unsigned l1i_misses_kernel; + unsigned l1i_hits_kernel; + unsigned long long l1r_hits_kernel; + unsigned long long l1r_misses_kernel; + unsigned long long l1w_hits_kernel; + unsigned long long l1w_misses_kernel; + unsigned long long shared_accesses_kernel; + unsigned long long cc_accesses_kernel; + unsigned long long dram_rd_kernel; + unsigned long long dram_wr_kernel; + unsigned long long dram_pre_kernel; + unsigned long long l2r_hits_kernel; + unsigned long long l2r_misses_kernel; + unsigned long long l2w_hits_kernel; + unsigned long long l2w_misses_kernel; + unsigned long long noc_tr_kernel; + unsigned long long noc_rc_kernel; + unsigned long long tot_inst_execution; + unsigned long long tot_int_inst_execution; + unsigned long long tot_fp_inst_execution; + unsigned long long commited_inst_execution; + unsigned long long ialu_acc_execution; + unsigned long long imul24_acc_execution; + unsigned long long imul32_acc_execution; + unsigned long long imul_acc_execution; + unsigned long long idiv_acc_execution; + unsigned long long dp_acc_execution; + unsigned long long dpmul_acc_execution; + unsigned long long dpdiv_acc_execution; + unsigned long long fp_acc_execution; + unsigned long long fpmul_acc_execution; + unsigned long long fpdiv_acc_execution; + unsigned long long sqrt_acc_execution; + unsigned long long log_acc_execution; + unsigned long long sin_acc_execution; + unsigned long long exp_acc_execution; + unsigned long long tensor_acc_execution; + unsigned long long tex_acc_execution; + unsigned long long tot_fpu_acc_execution; + unsigned long long tot_sfu_acc_execution; + unsigned long long tot_threads_acc_execution; + unsigned long long tot_warps_acc_execution; + unsigned long long sp_active_lanes_execution; + unsigned long long sfu_active_lanes_execution; + double get_total_inst(bool aggregate_stat) { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += (pwr_core_stat->m_num_decoded_insn[CURRENT_STAT_IDX][i]) - + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_decoded_insn[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_decoded_insn[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_decoded_insn[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_total_int_inst() { - unsigned total_inst = 0; + double get_total_int_inst(bool aggregate_stat) { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += + if(aggregate_stat) + total_inst += + (pwr_core_stat->m_num_INTdecoded_insn[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_INTdecoded_insn[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_INTdecoded_insn[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_total_fp_inst() { - unsigned total_inst = 0; + double get_total_fp_inst(bool aggregate_stat) { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += (pwr_core_stat->m_num_FPdecoded_insn[CURRENT_STAT_IDX][i]) - + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_FPdecoded_insn[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_FPdecoded_insn[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_FPdecoded_insn[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_total_load_inst() { - unsigned total_inst = 0; + double get_total_load_inst() { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { total_inst += (pwr_core_stat->m_num_loadqueued_insn[CURRENT_STAT_IDX][i]) - @@ -179,8 +246,8 @@ class power_stat_t { } return total_inst; } - unsigned get_total_store_inst() { - unsigned total_inst = 0; + double get_total_store_inst() { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { total_inst += (pwr_core_stat->m_num_storequeued_insn[CURRENT_STAT_IDX][i]) - @@ -188,34 +255,39 @@ class power_stat_t { } return total_inst; } - unsigned get_sp_committed_inst() { - unsigned total_inst = 0; + double get_sp_committed_inst() { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { total_inst += (pwr_core_stat->m_num_sp_committed[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_sp_committed[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_sfu_committed_inst() { - unsigned total_inst = 0; + double get_sfu_committed_inst() { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { total_inst += (pwr_core_stat->m_num_sfu_committed[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_sfu_committed[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_mem_committed_inst() { - unsigned total_inst = 0; + double get_mem_committed_inst() { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { total_inst += (pwr_core_stat->m_num_mem_committed[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_mem_committed[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_committed_inst() { - unsigned total_inst = 0; + double get_committed_inst(bool aggregate_stat) { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += (pwr_core_stat->m_num_mem_committed[CURRENT_STAT_IDX][i]) - + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_mem_committed[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_sfu_committed[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_sp_committed[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_mem_committed[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_mem_committed[PREV_STAT_IDX][i]) + (pwr_core_stat->m_num_sfu_committed[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_sfu_committed[PREV_STAT_IDX][i]) + @@ -224,19 +296,27 @@ class power_stat_t { } return total_inst; } - unsigned get_regfile_reads() { - unsigned total_inst = 0; + double get_regfile_reads(bool aggregate_stat) { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += + if(aggregate_stat) + total_inst += + (pwr_core_stat->m_read_regfile_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_read_regfile_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_read_regfile_acesses[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_regfile_writes() { - unsigned total_inst = 0; + double get_regfile_writes(bool aggregate_stat) { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += + if(aggregate_stat) + total_inst += + (pwr_core_stat->m_write_regfile_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_write_regfile_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_write_regfile_acesses[PREV_STAT_IDX][i]); } @@ -253,17 +333,20 @@ class power_stat_t { return total_inst; } - unsigned get_non_regfile_operands() { - unsigned total_inst = 0; + double get_non_regfile_operands(bool aggregate_stat) { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += (pwr_core_stat->m_non_rf_operands[CURRENT_STAT_IDX][i]) - + if(aggregate_stat) + total_inst += (pwr_core_stat->m_non_rf_operands[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_non_rf_operands[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_non_rf_operands[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_sp_accessess() { - unsigned total_inst = 0; + double get_sp_accessess() { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { total_inst += (pwr_core_stat->m_num_sp_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_sp_acesses[PREV_STAT_IDX][i]); @@ -271,25 +354,58 @@ class power_stat_t { return total_inst; } - unsigned get_sfu_accessess() { - unsigned total_inst = 0; + double get_sfu_accessess() { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { total_inst += (pwr_core_stat->m_num_sfu_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_sfu_acesses[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_trans_accessess() { - unsigned total_inst = 0; - for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += (pwr_core_stat->m_num_trans_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_trans_acesses[PREV_STAT_IDX][i]); - } - return total_inst; + + double get_sqrt_accessess(bool aggregate_stat){ + double total_inst=0; + for(unsigned i=0; inum_shader();i++){ + if(aggregate_stat) + total_inst+=(pwr_core_stat->m_num_sqrt_acesses[CURRENT_STAT_IDX][i]); + else + total_inst+=(pwr_core_stat->m_num_sqrt_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_sqrt_acesses[PREV_STAT_IDX][i]); + } + return total_inst; + } + double get_log_accessess(bool aggregate_stat){ + double total_inst=0; + for(unsigned i=0; inum_shader();i++){ + if(aggregate_stat) + total_inst+=(pwr_core_stat->m_num_log_acesses[CURRENT_STAT_IDX][i]); + else + total_inst+=(pwr_core_stat->m_num_log_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_log_acesses[PREV_STAT_IDX][i]); + } + return total_inst; + } + double get_sin_accessess(bool aggregate_stat){ + double total_inst=0; + for(unsigned i=0; inum_shader();i++){ + if(aggregate_stat) + total_inst+=(pwr_core_stat->m_num_sin_acesses[CURRENT_STAT_IDX][i]); + else + total_inst+=(pwr_core_stat->m_num_sin_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_sin_acesses[PREV_STAT_IDX][i]); + } + return total_inst; + } + double get_exp_accessess(bool aggregate_stat){ + double total_inst=0; + for(unsigned i=0; inum_shader();i++){ + if(aggregate_stat) + total_inst+=(pwr_core_stat->m_num_exp_acesses[CURRENT_STAT_IDX][i]); + else + total_inst+=(pwr_core_stat->m_num_exp_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_exp_acesses[PREV_STAT_IDX][i]); + } + return total_inst; } - unsigned get_mem_accessess() { - unsigned total_inst = 0; + double get_mem_accessess() { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { total_inst += (pwr_core_stat->m_num_mem_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_mem_acesses[PREV_STAT_IDX][i]); @@ -297,66 +413,164 @@ class power_stat_t { return total_inst; } - unsigned get_intdiv_accessess() { - unsigned total_inst = 0; + double get_intdiv_accessess(bool aggregate_stat) { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += (pwr_core_stat->m_num_idiv_acesses[CURRENT_STAT_IDX][i]) - + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_idiv_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_idiv_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_idiv_acesses[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_fpdiv_accessess() { - unsigned total_inst = 0; + double get_fpdiv_accessess(bool aggregate_stat) { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += (pwr_core_stat->m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]) - + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_fpdiv_acesses[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_intmul32_accessess() { - unsigned total_inst = 0; + double get_intmul32_accessess(bool aggregate_stat) { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += (pwr_core_stat->m_num_imul32_acesses[CURRENT_STAT_IDX][i]) - + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_imul32_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_imul32_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_imul32_acesses[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_intmul24_accessess() { - unsigned total_inst = 0; + double get_intmul24_accessess(bool aggregate_stat) { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += (pwr_core_stat->m_num_imul24_acesses[CURRENT_STAT_IDX][i]) - + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_imul24_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_imul24_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_imul24_acesses[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_intmul_accessess() { - unsigned total_inst = 0; - for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += (pwr_core_stat->m_num_imul_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_imul_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_imul24_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_imul24_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_imul32_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_imul32_acesses[PREV_STAT_IDX][i]); + double get_intmul_accessess(bool aggregate_stat){ + double total_inst=0; + for(unsigned i=0; inum_shader();i++){ + if(aggregate_stat) + total_inst+= (pwr_core_stat->m_num_imul_acesses[CURRENT_STAT_IDX][i]); + else + total_inst+= (pwr_core_stat->m_num_imul_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_imul_acesses[PREV_STAT_IDX][i]); + } + return total_inst; + } + + double get_fpmul_accessess(bool aggregate_stat){ + double total_inst=0; + for(unsigned i=0; inum_shader();i++){ + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_fpmul_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_fpmul_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_fpmul_acesses[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_fpmul_accessess() { - unsigned total_inst = 0; - for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += (pwr_core_stat->m_num_fp_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_fp_acesses[PREV_STAT_IDX][i]); + double get_fp_accessess(bool aggregate_stat){ + double total_inst=0; + for(unsigned i=0; inum_shader();i++){ + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_fp_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_fp_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_fp_acesses[PREV_STAT_IDX][i]); } return total_inst; } - float get_sp_active_lanes() { - unsigned total_inst = 0; + double get_dp_accessess(bool aggregate_stat){ + double total_inst=0; + for(unsigned i=0; inum_shader();i++){ + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_dp_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_dp_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_dp_acesses[PREV_STAT_IDX][i]); + } + return total_inst; + } + + double get_dpmul_accessess(bool aggregate_stat){ + double total_inst=0; + for(unsigned i=0; inum_shader();i++){ + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_dpmul_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_dpmul_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_dpmul_acesses[PREV_STAT_IDX][i]); + } + return total_inst; + } + + double get_dpdiv_accessess(bool aggregate_stat){ + double total_inst=0; + for(unsigned i=0; inum_shader();i++){ + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_dpdiv_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_dpdiv_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_dpdiv_acesses[PREV_STAT_IDX][i]); + } + return total_inst; + } + + double get_tensor_accessess(bool aggregate_stat){ + double total_inst=0; + for(unsigned i=0; inum_shader();i++){ + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_tensor_core_acesses[PREV_STAT_IDX][i]); + } + return total_inst; + } + + double get_const_accessess(bool aggregate_stat){ + double total_inst=0; + for(unsigned i=0; inum_shader();i++){ + if(aggregate_stat) + total_inst += pwr_core_stat->m_num_const_acesses[CURRENT_STAT_IDX][i]; + else + total_inst += (pwr_core_stat->m_num_const_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_const_acesses[PREV_STAT_IDX][i]); + } + return (total_inst); + } + + double get_tex_accessess(bool aggregate_stat){ + double total_inst=0; + for(unsigned i=0; inum_shader();i++){ + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_tex_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_tex_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_tex_acesses[PREV_STAT_IDX][i]); + } + return total_inst; + } + + double get_sp_active_lanes() { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { total_inst += (pwr_core_stat->m_active_sp_lanes[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_active_sp_lanes[PREV_STAT_IDX][i]); @@ -365,7 +579,7 @@ class power_stat_t { } float get_sfu_active_lanes() { - unsigned total_inst = 0; + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { total_inst += (pwr_core_stat->m_active_sfu_lanes[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_active_sfu_lanes[PREV_STAT_IDX][i]); @@ -375,49 +589,141 @@ class power_stat_t { m_config->gpgpu_num_sfu_units; } - unsigned get_tot_fpu_accessess() { - unsigned total_inst = 0; + + float get_active_threads(bool aggregate_stat) { + unsigned total_threads = 0; + unsigned total_warps = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if(aggregate_stat){ + total_threads += (pwr_core_stat->m_active_exu_threads[CURRENT_STAT_IDX][i]) ; + total_warps += (pwr_core_stat->m_active_exu_warps[CURRENT_STAT_IDX][i]); + } + else{ + total_threads += (pwr_core_stat->m_active_exu_threads[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_active_exu_threads[PREV_STAT_IDX][i]); + total_warps += (pwr_core_stat->m_active_exu_warps[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_active_exu_warps[PREV_STAT_IDX][i]); + } + } + if(total_warps != 0) + return (float)((float)total_threads / (float)total_warps); + else + return 0; + } + + unsigned long long get_tot_threads_kernel(bool aggregate_stat) { + unsigned total_threads = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += (pwr_core_stat->m_num_fp_acesses[CURRENT_STAT_IDX][i]) - + if(aggregate_stat){ + total_threads += (pwr_core_stat->m_active_exu_threads[CURRENT_STAT_IDX][i]) ; + } + else{ + total_threads += (pwr_core_stat->m_active_exu_threads[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_active_exu_threads[PREV_STAT_IDX][i]); + } + } + + return total_threads; + } + unsigned long long get_tot_warps_kernel(bool aggregate_stat) { + unsigned long long total_warps = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if(aggregate_stat){ + total_warps += (pwr_core_stat->m_active_exu_warps[CURRENT_STAT_IDX][i]); + } + else{ + total_warps += (pwr_core_stat->m_active_exu_warps[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_active_exu_warps[PREV_STAT_IDX][i]); + } + } + return total_warps; + } + + + double get_tot_fpu_accessess(bool aggregate_stat){ + double total_inst=0; + for(unsigned i=0; inum_shader();i++){ + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_fp_acesses[CURRENT_STAT_IDX][i])+ + (pwr_core_stat->m_num_dp_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_fp_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_fp_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_fpdiv_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_fpmul_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_fpmul_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_imul24_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_imul24_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_imul_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_imul_acesses[PREV_STAT_IDX][i]); + (pwr_core_stat->m_num_dp_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_dp_acesses[PREV_STAT_IDX][i]); } - total_inst += - get_total_load_inst() + get_total_store_inst() + get_tex_inst(); + //total_inst += get_total_load_inst()+get_total_store_inst()+get_tex_inst(); return total_inst; } - unsigned get_tot_sfu_accessess() { - unsigned total_inst = 0; - for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += (pwr_core_stat->m_num_idiv_acesses[CURRENT_STAT_IDX][i]) - + + + double get_tot_sfu_accessess(bool aggregate_stat){ + double total_inst=0; + for(unsigned i=0; inum_shader();i++){ + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_idiv_acesses[CURRENT_STAT_IDX][i])+ + (pwr_core_stat->m_num_imul32_acesses[CURRENT_STAT_IDX][i])+ + (pwr_core_stat->m_num_sqrt_acesses[CURRENT_STAT_IDX][i])+ + (pwr_core_stat->m_num_log_acesses[CURRENT_STAT_IDX][i])+ + (pwr_core_stat->m_num_sin_acesses[CURRENT_STAT_IDX][i])+ + (pwr_core_stat->m_num_exp_acesses[CURRENT_STAT_IDX][i])+ + (pwr_core_stat->m_num_fpdiv_acesses[CURRENT_STAT_IDX][i])+ + (pwr_core_stat->m_num_fpmul_acesses[CURRENT_STAT_IDX][i])+ + (pwr_core_stat->m_num_dpmul_acesses[CURRENT_STAT_IDX][i])+ + (pwr_core_stat->m_num_dpdiv_acesses[CURRENT_STAT_IDX][i])+ + (pwr_core_stat->m_num_imul24_acesses[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_imul_acesses[CURRENT_STAT_IDX][i])+ + (pwr_core_stat->m_num_tensor_core_acesses[CURRENT_STAT_IDX][i])+ + (pwr_core_stat->m_num_tex_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_idiv_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_idiv_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_imul32_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_imul32_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_imul32_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_trans_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_trans_acesses[PREV_STAT_IDX][i]); + (pwr_core_stat->m_num_sqrt_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_sqrt_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_log_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_log_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_sin_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_sin_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_exp_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_exp_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_fpdiv_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_fpmul_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_fpmul_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_dpmul_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_dpmul_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_dpdiv_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_dpdiv_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_imul24_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_imul24_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_imul_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_imul_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_tensor_core_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_tex_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_tex_acesses[PREV_STAT_IDX][i]); + } return total_inst; } - unsigned get_ialu_accessess() { - unsigned total_inst = 0; + double get_ialu_accessess(bool aggregate_stat) { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += (pwr_core_stat->m_num_ialu_acesses[CURRENT_STAT_IDX][i]) - + if(aggregate_stat) + total_inst += (pwr_core_stat->m_num_ialu_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_ialu_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_ialu_acesses[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_tex_inst() { - unsigned total_inst = 0; + double get_tex_inst() { + double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { total_inst += (pwr_core_stat->m_num_tex_inst[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_tex_inst[PREV_STAT_IDX][i]); @@ -425,7 +731,7 @@ class power_stat_t { return total_inst; } - unsigned get_constant_c_accesses() { + double get_constant_c_accesses() { enum mem_access_type access_type[] = {CONST_ACC_R}; enum cache_request_status request_status[] = {HIT, MISS, HIT_RESERVED}; unsigned num_access_type = @@ -440,7 +746,7 @@ class power_stat_t { access_type, num_access_type, request_status, num_request_status)); } - unsigned get_constant_c_misses() { + double get_constant_c_misses() { enum mem_access_type access_type[] = {CONST_ACC_R}; enum cache_request_status request_status[] = {MISS}; unsigned num_access_type = @@ -455,10 +761,10 @@ class power_stat_t { access_type, num_access_type, request_status, num_request_status)); } - unsigned get_constant_c_hits() { + double get_constant_c_hits() { return (get_constant_c_accesses() - get_constant_c_misses()); } - unsigned get_texture_c_accesses() { + double get_texture_c_accesses() { enum mem_access_type access_type[] = {TEXTURE_ACC_R}; enum cache_request_status request_status[] = {HIT, MISS, HIT_RESERVED}; unsigned num_access_type = @@ -473,7 +779,7 @@ class power_stat_t { access_type, num_access_type, request_status, num_request_status)); } - unsigned get_texture_c_misses() { + double get_texture_c_misses() { enum mem_access_type access_type[] = {TEXTURE_ACC_R}; enum cache_request_status request_status[] = {MISS}; unsigned num_access_type = @@ -488,205 +794,268 @@ class power_stat_t { access_type, num_access_type, request_status, num_request_status)); } - unsigned get_texture_c_hits() { + double get_texture_c_hits() { return (get_texture_c_accesses() - get_texture_c_misses()); } - unsigned get_inst_c_accesses() { + double get_inst_c_accesses(bool aggregate_stat) { enum mem_access_type access_type[] = {INST_ACC_R}; enum cache_request_status request_status[] = {HIT, MISS, HIT_RESERVED}; unsigned num_access_type = sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - - return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( + if(aggregate_stat) + return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); + else + return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)) - (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)); } - unsigned get_inst_c_misses() { + double get_inst_c_misses(bool aggregate_stat) { enum mem_access_type access_type[] = {INST_ACC_R}; enum cache_request_status request_status[] = {MISS}; unsigned num_access_type = sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - - return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( + if(aggregate_stat) + return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); + else + return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)) - (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)); } - unsigned get_inst_c_hits() { - return (get_inst_c_accesses() - get_inst_c_misses()); + double get_inst_c_hits(bool aggregate_stat) { + return (get_inst_c_accesses(aggregate_stat) - get_inst_c_misses(aggregate_stat)); } - unsigned get_l1d_read_accesses() { + double get_l1d_read_accesses(bool aggregate_stat) { enum mem_access_type access_type[] = {GLOBAL_ACC_R, LOCAL_ACC_R}; - enum cache_request_status request_status[] = {HIT, MISS, HIT_RESERVED}; + enum cache_request_status request_status[] = {HIT, MISS, SECTOR_MISS}; unsigned num_access_type = sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( + if(aggregate_stat){ + return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); + } + else{ + return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)) - (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)); + } + } + double get_l1d_read_misses(bool aggregate_stat) { + return (get_l1d_read_accesses(aggregate_stat) - get_l1d_read_hits(aggregate_stat)); } - unsigned get_l1d_read_misses() { + double get_l1d_read_hits(bool aggregate_stat) { enum mem_access_type access_type[] = {GLOBAL_ACC_R, LOCAL_ACC_R}; - enum cache_request_status request_status[] = {MISS}; + enum cache_request_status request_status[] = {HIT, MSHR_HIT}; unsigned num_access_type = sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( + if(aggregate_stat){ + return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); + } + else{ + return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)) - (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)); + } } - unsigned get_l1d_read_hits() { - return (get_l1d_read_accesses() - get_l1d_read_misses()); - } - unsigned get_l1d_write_accesses() { + double get_l1d_write_accesses(bool aggregate_stat) { enum mem_access_type access_type[] = {GLOBAL_ACC_W, LOCAL_ACC_W}; - enum cache_request_status request_status[] = {HIT, MISS, HIT_RESERVED}; + enum cache_request_status request_status[] = {HIT, MISS, SECTOR_MISS}; unsigned num_access_type = sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( + if(aggregate_stat){ + return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); + } + else{ + return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)) - (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)); + } + } + double get_l1d_write_misses(bool aggregate_stat) { + return (get_l1d_write_accesses(aggregate_stat) - get_l1d_write_hits(aggregate_stat)); } - unsigned get_l1d_write_misses() { + double get_l1d_write_hits(bool aggregate_stat) { enum mem_access_type access_type[] = {GLOBAL_ACC_W, LOCAL_ACC_W}; - enum cache_request_status request_status[] = {MISS}; + enum cache_request_status request_status[] = {HIT, MSHR_HIT}; unsigned num_access_type = sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( + if(aggregate_stat){ + return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); + } + else{ + return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)) - (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)); + } } - unsigned get_l1d_write_hits() { - return (get_l1d_write_accesses() - get_l1d_write_misses()); - } - unsigned get_cache_misses() { - return get_l1d_read_misses() + get_constant_c_misses() + - get_l1d_write_misses() + get_texture_c_misses(); + double get_cache_misses() { + return get_l1d_read_misses(0) + get_constant_c_misses() + + get_l1d_write_misses(0) + get_texture_c_misses(); } - unsigned get_cache_read_misses() { - return get_l1d_read_misses() + get_constant_c_misses() + + double get_cache_read_misses() { + return get_l1d_read_misses(0) + get_constant_c_misses() + get_texture_c_misses(); } - unsigned get_cache_write_misses() { return get_l1d_write_misses(); } + double get_cache_write_misses() { return get_l1d_write_misses(0); } - unsigned get_shmem_read_access() { + double get_shmem_access(bool aggregate_stat) { unsigned total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - total_inst += (pwr_mem_stat->shmem_read_access[CURRENT_STAT_IDX][i]) - - (pwr_mem_stat->shmem_read_access[PREV_STAT_IDX][i]); + if(aggregate_stat) + total_inst += (pwr_mem_stat->shmem_access[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_mem_stat->shmem_access[CURRENT_STAT_IDX][i]) - + (pwr_mem_stat->shmem_access[PREV_STAT_IDX][i]); } return total_inst; } - unsigned get_l2_read_accesses() { + unsigned long long get_l2_read_accesses(bool aggregate_stat) { enum mem_access_type access_type[] = { GLOBAL_ACC_R, LOCAL_ACC_R, CONST_ACC_R, TEXTURE_ACC_R, INST_ACC_R}; - enum cache_request_status request_status[] = {HIT, MISS, HIT_RESERVED}; + enum cache_request_status request_status[] = {HIT, HIT_RESERVED, MISS, SECTOR_MISS}; unsigned num_access_type = sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - - return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( + if(aggregate_stat){ + return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); + } + else{ + return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)) - (pwr_mem_stat->l2_cache_stats[PREV_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)); + } } - unsigned get_l2_read_misses() { - enum mem_access_type access_type[] = { + unsigned long long get_l2_read_misses(bool aggregate_stat) { + return (get_l2_read_accesses(aggregate_stat) - get_l2_read_hits(aggregate_stat)); + } + + unsigned long long get_l2_read_hits(bool aggregate_stat) { + enum mem_access_type access_type[] = { GLOBAL_ACC_R, LOCAL_ACC_R, CONST_ACC_R, TEXTURE_ACC_R, INST_ACC_R}; - enum cache_request_status request_status[] = {MISS}; + enum cache_request_status request_status[] = {HIT, HIT_RESERVED}; unsigned num_access_type = sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - - return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( + if(aggregate_stat){ + return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); + } + else{ + return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)) - (pwr_mem_stat->l2_cache_stats[PREV_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)); + } } - unsigned get_l2_read_hits() { - return (get_l2_read_accesses() - get_l2_read_misses()); - } - - unsigned get_l2_write_accesses() { + unsigned long long get_l2_write_accesses(bool aggregate_stat) { enum mem_access_type access_type[] = {GLOBAL_ACC_W, LOCAL_ACC_W, L1_WRBK_ACC}; - enum cache_request_status request_status[] = {HIT, MISS, HIT_RESERVED}; + enum cache_request_status request_status[] = {HIT, HIT_RESERVED, MISS, SECTOR_MISS}; unsigned num_access_type = sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - - return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( + if(aggregate_stat){ + return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); + } + else{ + return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)) - (pwr_mem_stat->l2_cache_stats[PREV_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)); + } } - unsigned get_l2_write_misses() { - enum mem_access_type access_type[] = {GLOBAL_ACC_W, LOCAL_ACC_W, + unsigned long long get_l2_write_misses(bool aggregate_stat) { + return (get_l2_write_accesses(aggregate_stat) - get_l2_write_hits(aggregate_stat)); + } + unsigned long long get_l2_write_hits(bool aggregate_stat) { + enum mem_access_type access_type[] = {GLOBAL_ACC_W, LOCAL_ACC_W, L1_WRBK_ACC}; - enum cache_request_status request_status[] = {MISS}; + enum cache_request_status request_status[] = {HIT, HIT_RESERVED}; unsigned num_access_type = sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - - return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( + if(aggregate_stat){ + return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); + } + else{ + return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)) - (pwr_mem_stat->l2_cache_stats[PREV_STAT_IDX].get_stats( access_type, num_access_type, request_status, num_request_status)); + } } - unsigned get_l2_write_hits() { - return (get_l2_write_accesses() - get_l2_write_misses()); - } - unsigned get_dram_cmd() { + double get_dram_cmd() { unsigned total = 0; for (unsigned i = 0; i < m_mem_config->m_n_mem; ++i) { total += (pwr_mem_stat->n_cmd[CURRENT_STAT_IDX][i] - @@ -694,7 +1063,7 @@ class power_stat_t { } return total; } - unsigned get_dram_activity() { + double get_dram_activity() { unsigned total = 0; for (unsigned i = 0; i < m_mem_config->m_n_mem; ++i) { total += (pwr_mem_stat->n_activity[CURRENT_STAT_IDX][i] - @@ -702,7 +1071,7 @@ class power_stat_t { } return total; } - unsigned get_dram_nop() { + double get_dram_nop() { unsigned total = 0; for (unsigned i = 0; i < m_mem_config->m_n_mem; ++i) { total += (pwr_mem_stat->n_nop[CURRENT_STAT_IDX][i] - @@ -710,7 +1079,7 @@ class power_stat_t { } return total; } - unsigned get_dram_act() { + double get_dram_act() { unsigned total = 0; for (unsigned i = 0; i < m_mem_config->m_n_mem; ++i) { total += (pwr_mem_stat->n_act[CURRENT_STAT_IDX][i] - @@ -718,31 +1087,49 @@ class power_stat_t { } return total; } - unsigned get_dram_pre() { + double get_dram_pre(bool aggregate_stat) { unsigned total = 0; for (unsigned i = 0; i < m_mem_config->m_n_mem; ++i) { - total += (pwr_mem_stat->n_pre[CURRENT_STAT_IDX][i] - + if(aggregate_stat){ + total += pwr_mem_stat->n_pre[CURRENT_STAT_IDX][i]; + } + else{ + total += (pwr_mem_stat->n_pre[CURRENT_STAT_IDX][i] - pwr_mem_stat->n_pre[PREV_STAT_IDX][i]); + } } return total; } - unsigned get_dram_rd() { + double get_dram_rd(bool aggregate_stat) { unsigned total = 0; for (unsigned i = 0; i < m_mem_config->m_n_mem; ++i) { - total += (pwr_mem_stat->n_rd[CURRENT_STAT_IDX][i] - + if(aggregate_stat){ + total += pwr_mem_stat->n_rd[CURRENT_STAT_IDX][i]; + } + else{ + total += (pwr_mem_stat->n_rd[CURRENT_STAT_IDX][i] - pwr_mem_stat->n_rd[PREV_STAT_IDX][i]); + } } return total; } - unsigned get_dram_wr() { + double get_dram_wr(bool aggregate_stat) { unsigned total = 0; for (unsigned i = 0; i < m_mem_config->m_n_mem; ++i) { - total += (pwr_mem_stat->n_wr[CURRENT_STAT_IDX][i] - - pwr_mem_stat->n_wr[PREV_STAT_IDX][i]); + if(aggregate_stat){ + total += pwr_mem_stat->n_wr[CURRENT_STAT_IDX][i] + + pwr_mem_stat->n_wr_WB[CURRENT_STAT_IDX][i]; + } + else{ + total += (pwr_mem_stat->n_wr[CURRENT_STAT_IDX][i] - + pwr_mem_stat->n_wr[PREV_STAT_IDX][i]) + + (pwr_mem_stat->n_wr_WB[CURRENT_STAT_IDX][i] - + pwr_mem_stat->n_wr_WB[PREV_STAT_IDX][i]); + } } return total; } - unsigned get_dram_req() { + double get_dram_req() { unsigned total = 0; for (unsigned i = 0; i < m_mem_config->m_n_mem; ++i) { total += (pwr_mem_stat->n_req[CURRENT_STAT_IDX][i] - @@ -751,20 +1138,31 @@ class power_stat_t { return total; } - long get_icnt_simt_to_mem() { + unsigned long long get_icnt_simt_to_mem(bool aggregate_stat) { long total = 0; - for (unsigned i = 0; i < m_config->n_simt_clusters; ++i) { - total += (pwr_mem_stat->n_simt_to_mem[CURRENT_STAT_IDX][i] - + for (unsigned i = 0; i < m_config->n_simt_clusters; ++i){ + if(aggregate_stat){ + total += pwr_mem_stat->n_simt_to_mem[CURRENT_STAT_IDX][i]; + } + else{ + total += (pwr_mem_stat->n_simt_to_mem[CURRENT_STAT_IDX][i] - pwr_mem_stat->n_simt_to_mem[PREV_STAT_IDX][i]); + } } return total; } - long get_icnt_mem_to_simt() { + unsigned long long get_icnt_mem_to_simt(bool aggregate_stat) { long total = 0; for (unsigned i = 0; i < m_config->n_simt_clusters; ++i) { - total += (pwr_mem_stat->n_mem_to_simt[CURRENT_STAT_IDX][i] - + if(aggregate_stat){ + total += pwr_mem_stat->n_mem_to_simt[CURRENT_STAT_IDX][i]; + } + + else{ + total += (pwr_mem_stat->n_mem_to_simt[CURRENT_STAT_IDX][i] - pwr_mem_stat->n_mem_to_simt[PREV_STAT_IDX][i]); + } } return total; } -- cgit v1.3 From 011891abfae060903f76d5c7aee23208cd295e71 Mon Sep 17 00:00:00 2001 From: JRPAN <25518778+JRPan@users.noreply.github.com> Date: Tue, 1 Feb 2022 20:36:24 -0500 Subject: Update Copyrights --- src/abstract_hardware_model.cc | 5 +++-- src/abstract_hardware_model.h | 5 +++-- src/cuda-sim/cuda-sim.cc | 5 +++-- src/cuda-sim/instructions.cc | 5 +++-- src/cuda-sim/ptx.l | 5 +++-- src/cuda-sim/ptx_ir.cc | 5 +++-- src/gpgpu-sim/dram.cc | 5 +++-- src/gpgpu-sim/dram.h | 5 +++-- src/gpgpu-sim/gpu-cache.cc | 6 ++++-- src/gpgpu-sim/gpu-cache.h | 5 +++-- src/gpgpu-sim/gpu-sim.cc | 5 +++-- src/gpgpu-sim/gpu-sim.h | 3 ++- src/gpgpu-sim/l2cache.cc | 5 +++-- src/gpgpu-sim/l2cache.h | 5 +++-- src/gpgpu-sim/power_interface.cc | 5 +++-- src/gpgpu-sim/power_interface.h | 5 +++-- src/gpgpu-sim/power_stat.cc | 5 +++-- src/gpgpu-sim/power_stat.h | 5 +++-- src/gpgpu-sim/shader.cc | 5 +++-- src/gpgpu-sim/shader.h | 5 +++-- 20 files changed, 60 insertions(+), 39 deletions(-) (limited to 'src/gpgpu-sim/power_stat.h') diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index 208047e..fda84e8 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Inderpreet Singh, Timothy Rogers, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Inderpreet Singh, Timothy Rogers, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index f04741f..e9d7c76 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Inderpreet Singh, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Inderpreet Singh, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index f9e5db3..680ce79 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Ali Bakhoda, Wilson W.L. Fung, -// George L. Yuan, Jimmy Kwa, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// George L. Yuan, Jimmy Kwa, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 44afbe5..e22d88a 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda, -// Jimmy Kwa, George L. Yuan, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Jimmy Kwa, George L. Yuan, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 7706f0b..15b3cf7 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -1,6 +1,7 @@ /* -Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas -The University of British Columbia, Northwestern University +Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas, +Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +The University of British Columbia, Northwestern University, Purdue University All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 2edc1ed..029cf73 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Ali Bakhoda, Wilson W.L. Fung, -// George L. Yuan, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// George L. Yuan, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index 545c45d..662c2ed 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda, -// Ivan Sham, George L. Yuan, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Ivan Sham, George L. Yuan, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index 88e46ed..90ea3e4 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Ivan Sham, Ali Bakhoda, -// George L. Yuan, Wilson W.L. Fung, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// George L. Yuan, Wilson W.L. Fung, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index a2aeec5..3a5a67d 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -1,5 +1,7 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, +// Vijay Kandiah, Nikos Hardavellas, Mahmoud Khairy, Junrui Pan, +// Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 498dfeb..4bbf7e2 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index e44551e..ee243c1 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, George L. Yuan, -// Ali Bakhoda, Andrew Turner, Ivan Sham, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Ali Bakhoda, Andrew Turner, Ivan Sham, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 68b3dfa..de69ef8 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -1,5 +1,6 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index 511c15e..44d793c 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index 902a4b7..7fa1f29 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/power_interface.cc b/src/gpgpu-sim/power_interface.cc index 63b9852..470f2f9 100644 --- a/src/gpgpu-sim/power_interface.cc +++ b/src/gpgpu-sim/power_interface.cc @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/power_interface.h b/src/gpgpu-sim/power_interface.h index 1a48894..1c6c510 100644 --- a/src/gpgpu-sim/power_interface.h +++ b/src/gpgpu-sim/power_interface.h @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/power_stat.cc b/src/gpgpu-sim/power_stat.cc index fd7a775..d0e673c 100644 --- a/src/gpgpu-sim/power_stat.cc +++ b/src/gpgpu-sim/power_stat.cc @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/power_stat.h b/src/gpgpu-sim/power_stat.h index e2c3ed5..d40f1d9 100644 --- a/src/gpgpu-sim/power_stat.h +++ b/src/gpgpu-sim/power_stat.h @@ -1,5 +1,6 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index c0161dd..9f8a129 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda, -// George L. Yuan, Andrew Turner, Inderpreet Singh, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// George L. Yuan, Andrew Turner, Inderpreet Singh, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 65d5625..d80476f 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1,6 +1,7 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Andrew Turner, -// Ali Bakhoda, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University +// Ali Bakhoda, Vijay Kandiah, Nikos Hardavellas, +// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers +// The University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without -- cgit v1.3