From b0cf792926caf74b393a14e36de676c7afd68164 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Tue, 12 Oct 2010 00:46:24 -0800 Subject: 1. adding simt_core_cluster, which models a TPC or (for fermi) GPC... this gives us a place to stick caches shared among shader cores but on the shader side of the interconnect... maybe move the clock boundary code here? after integrating booksim 2 code? 2. added a pending write table to ldst_unit rather than scoreboard ... rationale is that ld/st unit needs to process register writes once it is done it can notify scoreboard once. 3. re-enabled shared memory delay (use pipeline within ldst_unit) 4. re-enabling operand collector writeback for all instruction types 5. disable MSHRs in this change list passing CUDA 3.1 regression next? texture cache, then redo mshrs? [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845] --- src/gpgpu-sim/scoreboard.cc | 44 +++++++++++++++----------------------------- 1 file changed, 15 insertions(+), 29 deletions(-) (limited to 'src/gpgpu-sim/scoreboard.cc') diff --git a/src/gpgpu-sim/scoreboard.cc b/src/gpgpu-sim/scoreboard.cc index 3484714..f3029f1 100644 --- a/src/gpgpu-sim/scoreboard.cc +++ b/src/gpgpu-sim/scoreboard.cc @@ -19,61 +19,47 @@ Scoreboard::Scoreboard( unsigned sid, unsigned n_warps ) } // Print scoreboard contents -void Scoreboard::printContents() +void Scoreboard::printContents() const { printf("scoreboard contents (sid=%d): \n", m_sid); for(unsigned i=0; i::iterator it; - for ( it=reg_table[i].begin() ; it != reg_table[i].end(); it++ ) - printf("%d ", *it); + printf(" wid = %2d: ", i); + std::set::const_iterator it; + for( it=reg_table[i].begin() ; it != reg_table[i].end(); it++ ) + printf("%u ", *it); printf("\n"); } } - -// Mark register as write-pending void Scoreboard::reserveRegister(unsigned wid, unsigned regnum) { if( !(reg_table[wid].find(regnum) == reg_table[wid].end()) ){ printf("Error: trying to reserve an already reserved register (sid=%d, wid=%d, regnum=%d).", m_sid, wid, regnum); - assert(reg_table[wid].find(regnum) == reg_table[wid].end()); + abort(); } - reg_table[wid].insert(regnum); } - // Unmark register as write-pending void Scoreboard::releaseRegister(unsigned wid, unsigned regnum) { - if( !(reg_table[wid].find(regnum) != reg_table[wid].end()) ) { - printf("Error: trying to release an unreserved register (sid=%d, wid=%d, regnum=%d).", m_sid, wid, regnum); - assert(reg_table[wid].find(regnum) != reg_table[wid].end()); - } + if( !(reg_table[wid].find(regnum) != reg_table[wid].end()) ) + return; reg_table[wid].erase(regnum); } - -// Reserve registers for an instruction -void Scoreboard::reserveRegisters(unsigned wid, const class inst_t* inst) +void Scoreboard::reserveRegisters(const class warp_inst_t* inst) { - // Reserve registers - if(inst->out[0] > 0) reserveRegister(wid, inst->out[0]); - if(inst->out[1] > 0) reserveRegister(wid, inst->out[1]); - if(inst->out[2] > 0) reserveRegister(wid, inst->out[2]); - if(inst->out[3] > 0) reserveRegister(wid, inst->out[3]); + for( unsigned r=0; r < 4; r++) + if(inst->out[r] > 0) reserveRegister(inst->warp_id(), inst->out[r]); } // Release registers for an instruction void Scoreboard::releaseRegisters(const class warp_inst_t *inst) { - unsigned wid = inst->warp_id(); - if(inst->out[0] > 0) releaseRegister(wid, inst->out[0]); - if(inst->out[1] > 0) releaseRegister(wid, inst->out[1]); - if(inst->out[2] > 0) releaseRegister(wid, inst->out[2]); - if(inst->out[3] > 0) releaseRegister(wid, inst->out[3]); + for( unsigned r=0; r < 4; r++) + if(inst->out[r] > 0) releaseRegister(inst->warp_id(), inst->out[r]); } /** @@ -82,7 +68,7 @@ void Scoreboard::releaseRegisters(const class warp_inst_t *inst) * @return * true if WAW or RAW hazard (no WAR since in-order issue) **/ -bool Scoreboard::checkCollision( unsigned wid, const class inst_t *inst ) +bool Scoreboard::checkCollision( unsigned wid, const class inst_t *inst ) const { // Get list of all input and output registers std::set inst_regs; @@ -100,7 +86,7 @@ bool Scoreboard::checkCollision( unsigned wid, const class inst_t *inst ) if(inst->ar2 > 0) inst_regs.insert(inst->ar2); // Check for collision, get the intersection of reserved registers and instruction registers - std::set::iterator it2; + std::set::const_iterator it2; for ( it2=inst_regs.begin() ; it2 != inst_regs.end(); it2++ ) if(reg_table[wid].find(*it2) != reg_table[wid].end()) { return true; -- cgit v1.3