From 615f173c25883fbc8db0363279e2eb216acb8c7e Mon Sep 17 00:00:00 2001 From: JRPAN <25518778+JRPan@users.noreply.github.com> Date: Sat, 20 Feb 2021 16:03:42 -0500 Subject: store ack for new waps --- src/gpgpu-sim/shader.cc | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/gpgpu-sim/shader.cc') diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 14d9044..4769ca8 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1974,6 +1974,18 @@ void ldst_unit::L1_latency_queue_cycle() { } else { assert(status == MISS || status == HIT_RESERVED); l1_latency_queue[j][0] = NULL; + if (mf_next->get_inst().is_store() && + (m_config->m_L1D_config.get_write_allocate_policy() == FETCH_ON_WRITE || + m_config->m_L1D_config.get_write_allocate_policy() == LAZY_FETCH_ON_READ) && + !was_writeallocate_sent(events)) { + unsigned dec_ack = + (m_config->m_L1D_config.get_mshr_type() == SECTOR_ASSOC) + ? (mf_next->get_data_size() / SECTOR_SIZE) + : 1; + mf_next->set_reply(); + for (unsigned i = 0; i < dec_ack; ++i) m_core->store_ack(mf_next); + if (!write_sent && !read_sent) delete mf_next; + } } } -- cgit v1.3 From ad7204189b79be89575d969b305c529a31a2a765 Mon Sep 17 00:00:00 2001 From: JRPAN <25518778+JRPan@users.noreply.github.com> Date: Tue, 2 Mar 2021 16:30:27 -0500 Subject: sending cache block byte mask --- src/abstract_hardware_model.h | 6 ++++++ src/gpgpu-sim/gpu-cache.cc | 21 ++++++++++++++++----- src/gpgpu-sim/gpu-cache.h | 28 ++++++++++++++++++++++++++++ src/gpgpu-sim/l2cache.cc | 14 ++++++++++++++ src/gpgpu-sim/l2cache.h | 6 ++++++ src/gpgpu-sim/shader.cc | 15 +++++++++++++++ src/gpgpu-sim/shader.h | 6 ++++++ 7 files changed, 91 insertions(+), 5 deletions(-) (limited to 'src/gpgpu-sim/shader.cc') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 982e416..e09acdb 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -869,6 +869,12 @@ class mem_fetch_allocator { virtual mem_fetch *alloc(const class warp_inst_t &inst, const mem_access_t &access, unsigned long long cycle) const = 0; + virtual mem_fetch *alloc(new_addr_type addr, mem_access_type type, + const active_mask_t &active_mask, + const mem_access_byte_mask_t &byte_mask, + const mem_access_sector_mask_t §or_mask, + unsigned size, bool wr, + unsigned long long cycle) const = 0; }; // the maximum number of destination, source, or address uarch operands in a diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 763705f..ded8004 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -358,8 +358,13 @@ enum cache_request_status tag_array::access(new_addr_type addr, unsigned time, if (m_config.m_alloc_policy == ON_MISS) { if (m_lines[idx]->is_modified_line()) { wb = true; + ((sector_cache_block *)m_lines[idx])->set_byte_mask(mf); evicted.set_info(m_lines[idx]->m_block_addr, - m_lines[idx]->get_modified_size()); + m_lines[idx]->get_modified_size(), + ((sector_cache_block *)m_lines[idx]) + ->get_byte_mask(), + ((sector_cache_block *)m_lines[idx]) + ->get_sector_mask()); } m_lines[idx]->allocate(m_config.tag(addr), m_config.block_addr(addr), time, mf->get_access_sector_mask()); @@ -1464,6 +1469,8 @@ enum cache_request_status data_cache::wr_miss_wa_lazy_fetch_on_read( m_tag_array->access(block_addr, time, cache_index, wb, evicted, mf); assert(m_status != HIT); cache_block_t *block = m_tag_array->get_block(cache_index); + block->set_status(MODIFIED, mf->get_access_sector_mask()); + ((sector_cache_block *)block)->set_byte_mask(mf); if (m_status == HIT_RESERVED) { block->set_ignore_on_fill(true, mf->get_access_sector_mask()); block->set_modified_on_fill(true, mf->get_access_sector_mask()); @@ -1484,8 +1491,10 @@ enum cache_request_status data_cache::wr_miss_wa_lazy_fetch_on_read( // (already modified lower level) if (wb && (m_config.m_write_policy != WRITE_THROUGH)) { mem_fetch *wb = m_memfetch_creator->alloc( - evicted.m_block_addr, m_wrbk_type, evicted.m_modified_size, true, - m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); + evicted.m_block_addr,m_wrbk_type, + mf->get_access_warp_mask(), evicted.m_byte_mask, + evicted.m_sector_mask, evicted.m_modified_size, + true, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); // the evicted block may have wrong chip id when advanced L2 hashing is // used, so set the right chip address from the original mf wb->set_chip(mf->get_tlx_addr().chip); @@ -1560,8 +1569,10 @@ enum cache_request_status data_cache::rd_miss_base( // (already modified lower level) if (wb && (m_config.m_write_policy != WRITE_THROUGH)) { mem_fetch *wb = m_memfetch_creator->alloc( - evicted.m_block_addr, m_wrbk_type, evicted.m_modified_size, true, - m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); + evicted.m_block_addr,m_wrbk_type, + mf->get_access_warp_mask(), evicted.m_byte_mask, + evicted.m_sector_mask, evicted.m_modified_size, + true, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); // the evicted block may have wrong chip id when advanced L2 hashing is // used, so set the right chip address from the original mf wb->set_chip(mf->get_tlx_addr().chip); diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 381ce94..042c1d6 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -72,14 +72,26 @@ enum cache_event_type { struct evicted_block_info { new_addr_type m_block_addr; unsigned m_modified_size; + mem_access_byte_mask_t m_byte_mask; + mem_access_sector_mask_t m_sector_mask; evicted_block_info() { m_block_addr = 0; m_modified_size = 0; + m_byte_mask.reset(); + m_sector_mask.reset(); } void set_info(new_addr_type block_addr, unsigned modified_size) { m_block_addr = block_addr; m_modified_size = modified_size; } + void set_info(new_addr_type block_addr, unsigned modified_size, + mem_access_byte_mask_t byte_mask, + mem_access_sector_mask_t sector_mask) { + m_block_addr = block_addr; + m_modified_size = modified_size; + m_byte_mask = byte_mask; + m_sector_mask = sector_mask; + } }; struct cache_event { @@ -251,6 +263,7 @@ struct sector_cache_block : public cache_block_t { m_line_alloc_time = 0; m_line_last_access_time = 0; m_line_fill_time = 0; + m_byte_mask.reset(); } virtual void allocate(new_addr_type tag, new_addr_type block_addr, @@ -362,6 +375,20 @@ struct sector_cache_block : public cache_block_t { m_status[sidx] = status; } + virtual void set_byte_mask(mem_fetch *mf) { + m_byte_mask = m_byte_mask | mf->get_access_byte_mask();; + } + virtual mem_access_byte_mask_t get_byte_mask() { + return m_byte_mask; + } + virtual mem_access_sector_mask_t get_sector_mask() { + mem_access_sector_mask_t sector_mask; + for (unsigned i = 0; i < SECTOR_CHUNCK_SIZE; i++) { + if (m_status[i] == MODIFIED) + sector_mask.set(i); + } + return sector_mask; + } virtual unsigned long long get_last_access_time() { return m_line_last_access_time; } @@ -429,6 +456,7 @@ struct sector_cache_block : public cache_block_t { bool m_set_modified_on_fill[SECTOR_CHUNCK_SIZE]; bool m_set_readable_on_fill[SECTOR_CHUNCK_SIZE]; bool m_readable[SECTOR_CHUNCK_SIZE]; + mem_access_byte_mask_t m_byte_mask; unsigned get_sector_index(mem_access_sector_mask_t sector_mask) { assert(sector_mask.count() == 1); diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index ab6e5c2..cd04af5 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -57,6 +57,20 @@ mem_fetch *partition_mf_allocator::alloc(new_addr_type addr, return mf; } +mem_fetch *partition_mf_allocator::alloc(new_addr_type addr, + mem_access_type type, + const active_mask_t &active_mask, + const mem_access_byte_mask_t &byte_mask, + const mem_access_sector_mask_t §or_mask, + unsigned size, bool wr, + unsigned long long cycle) const { + mem_access_t access(type, addr, size, wr, active_mask, byte_mask, + sector_mask, m_memory_config->gpgpu_ctx); + mem_fetch *mf = + new mem_fetch(access, NULL, wr ? WRITE_PACKET_SIZE : READ_PACKET_SIZE, -1, + -1, -1, m_memory_config, cycle); + return mf; +} memory_partition_unit::memory_partition_unit(unsigned partition_id, const memory_config *config, class memory_stats_t *stats, diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index 3152db3..1f5d7c4 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -51,6 +51,12 @@ class partition_mf_allocator : public mem_fetch_allocator { virtual mem_fetch *alloc(new_addr_type addr, mem_access_type type, unsigned size, bool wr, unsigned long long cycle) const; + virtual mem_fetch *alloc(new_addr_type addr, mem_access_type type, + const active_mask_t &active_mask, + const mem_access_byte_mask_t &byte_mask, + const mem_access_sector_mask_t §or_mask, + unsigned size, bool wr, + unsigned long long cycle) const; private: const memory_config *m_memory_config; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 4769ca8..4b4c98d 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -61,6 +61,21 @@ mem_fetch *shader_core_mem_fetch_allocator::alloc( m_core_id, m_cluster_id, m_memory_config, cycle); return mf; } + +mem_fetch *shader_core_mem_fetch_allocator::alloc( + new_addr_type addr, mem_access_type type, + const active_mask_t &active_mask, + const mem_access_byte_mask_t &byte_mask, + const mem_access_sector_mask_t §or_mask, + unsigned size, bool wr, + unsigned long long cycle) const { + mem_access_t access(type, addr, size, wr, active_mask, byte_mask, + sector_mask, m_memory_config->gpgpu_ctx); + mem_fetch *mf = + new mem_fetch(access, NULL, wr ? WRITE_PACKET_SIZE : READ_PACKET_SIZE, -1, + m_core_id, m_cluster_id, m_memory_config, cycle); + return mf; + } ///////////////////////////////////////////////////////////////////////////// std::list shader_core_ctx::get_regs_written(const inst_t &fvt) const { diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 8c02fd7..a7a2c02 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1872,6 +1872,12 @@ class shader_core_mem_fetch_allocator : public mem_fetch_allocator { } mem_fetch *alloc(new_addr_type addr, mem_access_type type, unsigned size, bool wr, unsigned long long cycle) const; + mem_fetch *alloc(new_addr_type addr, mem_access_type type, + const active_mask_t &active_mask, + const mem_access_byte_mask_t &byte_mask, + const mem_access_sector_mask_t §or_mask, + unsigned size, bool wr, + unsigned long long cycle) const; mem_fetch *alloc(const warp_inst_t &inst, const mem_access_t &access, unsigned long long cycle) const { warp_inst_t inst_copy = inst; -- cgit v1.3 From 0601354a4d7f7f106e008b47cbc74097ec0a2a69 Mon Sep 17 00:00:00 2001 From: JRPAN <25518778+JRPan@users.noreply.github.com> Date: Tue, 18 May 2021 14:35:04 -0400 Subject: Add WT to lazy_fetch_on_read --- src/gpgpu-sim/gpu-cache.cc | 29 ++++++++++++++++++++++++++--- src/gpgpu-sim/gpu-cache.h | 3 +++ src/gpgpu-sim/shader.cc | 5 +++-- 3 files changed, 32 insertions(+), 5 deletions(-) (limited to 'src/gpgpu-sim/shader.cc') diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 9e1db8b..390bacc 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -1494,16 +1494,39 @@ enum cache_request_status data_cache::wr_miss_wa_lazy_fetch_on_read( new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list &events, enum cache_request_status status) { new_addr_type block_addr = m_config.block_addr(addr); + new_addr_type mshr_addr = m_config.mshr_addr(mf->get_addr()); // if the request writes to the whole cache line/sector, then, write and set // cache line Modified. and no need to send read request to memory or reserve // mshr - if (miss_queue_full(0)) { - m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL); - return RESERVATION_FAIL; // cannot handle request this cycle + // Write allocate, maximum 2 requests (write miss, write back request) + // Conservatively ensure the worst-case request can be handled this + // cycle + if (m_config.m_write_policy == WRITE_THROUGH) { + bool mshr_hit = m_mshrs.probe(mshr_addr); + bool mshr_avail = !m_mshrs.full(mshr_addr); + if (miss_queue_full(1) || + (!(mshr_hit && mshr_avail) && + !(!mshr_hit && mshr_avail && + (m_miss_queue.size() < m_config.m_miss_queue_size)))) { + // check what is the exactly the failure reason + if (miss_queue_full(1)) + m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL); + else if (mshr_hit && !mshr_avail) + m_stats.inc_fail_stats(mf->get_access_type(), MSHR_MERGE_ENRTY_FAIL); + else if (!mshr_hit && !mshr_avail) + m_stats.inc_fail_stats(mf->get_access_type(), MSHR_ENRTY_FAIL); + else + assert(0); + + return RESERVATION_FAIL; + } + + send_write_request(mf, cache_event(WRITE_REQUEST_SENT), time, events); } + bool wb = false; evicted_block_info evicted; diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index c2e302e..6811b86 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -821,6 +821,9 @@ class cache_config { write_allocate_policy_t get_write_allocate_policy() { return m_write_alloc_policy; } + write_policy_t get_write_policy() { + return m_write_policy; + } protected: void exit_parse_error() { diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 4b4c98d..22bd8e9 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1989,9 +1989,10 @@ void ldst_unit::L1_latency_queue_cycle() { } else { assert(status == MISS || status == HIT_RESERVED); l1_latency_queue[j][0] = NULL; - if (mf_next->get_inst().is_store() && + if (m_config->m_L1D_config.get_write_policy() != WRITE_THROUGH && + mf_next->get_inst().is_store() && (m_config->m_L1D_config.get_write_allocate_policy() == FETCH_ON_WRITE || - m_config->m_L1D_config.get_write_allocate_policy() == LAZY_FETCH_ON_READ) && + m_config->m_L1D_config.get_write_allocate_policy() == LAZY_FETCH_ON_READ) && !was_writeallocate_sent(events)) { unsigned dec_ack = (m_config->m_L1D_config.get_mshr_type() == SECTOR_ASSOC) -- cgit v1.3 From a2b1b1c2839fe3fc05a0cae126204120fab00f62 Mon Sep 17 00:00:00 2001 From: JRPAN <25518778+JRPan@users.noreply.github.com> Date: Mon, 17 May 2021 17:35:53 -0400 Subject: adaptive cache - update --- src/abstract_hardware_model.h | 2 +- src/gpgpu-sim/gpu-cache.h | 11 +++++ src/gpgpu-sim/shader.cc | 95 +++++++++++++++++++++++++------------------ 3 files changed, 68 insertions(+), 40 deletions(-) (limited to 'src/gpgpu-sim/shader.cc') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index e796571..bd10a93 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -65,7 +65,7 @@ enum FuncCache { FuncCachePreferL1 = 2 }; -enum AdaptiveCache { FIXED = 0, ADAPTIVE_VOLTA = 1 }; +enum AdaptiveCache { FIXED = 0, ADAPTIVE_CACHE = 1 }; #ifdef __cplusplus diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index ccc935b..0162b6c 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -616,6 +616,8 @@ class cache_config { m_atom_sz = (m_cache_type == SECTOR) ? SECTOR_SIZE : m_line_sz; m_sector_sz_log2 = LOGB2(SECTOR_SIZE); original_m_assoc = m_assoc; + original_sz = m_nset * original_m_assoc * m_line_sz; + // For more details about difference between FETCH_ON_WRITE and WRITE // VALIDAE policies Read: Jouppi, Norman P. "Cache write policies and @@ -710,6 +712,14 @@ class cache_config { assert(m_valid); return MAX_DEFAULT_CACHE_SIZE_MULTIBLIER * original_m_assoc; } + unsigned get_original_assoc() const { + assert(m_valid); + return original_m_assoc; + } + unsigned get_original_sz() const { + assert(m_valid); + return original_sz; + } void print(FILE *fp) const { fprintf(fp, "Size = %d B (%d Set x %d-way x %d byte line)\n", m_line_sz * m_nset * m_assoc, m_nset, m_assoc, m_line_sz); @@ -777,6 +787,7 @@ class cache_config { unsigned m_atom_sz; unsigned m_sector_sz_log2; unsigned original_m_assoc; + unsigned original_sz; bool m_is_streaming; enum replacement_policy_t m_replacement_policy; // 'L' = LRU, 'F' = FIFO diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 14d9044..b2adb4f 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3292,50 +3292,67 @@ unsigned int shader_core_config::max_cta(const kernel_info_t &k) const { if (adaptive_cache_config && !k.cache_config_set) { // For more info about adaptive cache, see // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x - unsigned total_shmed = kernel_info->smem * result; - assert(total_shmed >= 0 && total_shmed <= gpgpu_shmem_size); - // assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared - // assert(m_L1D_config.get_nset() == 4); //Volta L1 has four sets - if (total_shmed < gpgpu_shmem_size) { - switch (adaptive_cache_config) { - case FIXED: - break; - case ADAPTIVE_VOLTA: { - // For Volta, we assign the remaining shared memory to L1 cache - // For more info about adaptive cache, see - // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x - // assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared - - // To Do: make it flexible and not tuned to 9KB share memory - unsigned max_assoc = m_L1D_config.get_max_assoc(); - if (total_shmed == 0) - m_L1D_config.set_assoc(max_assoc); // L1 is 128KB and shd=0 - else if (total_shmed > 0 && total_shmed <= 8192) - m_L1D_config.set_assoc(0.9375 * - max_assoc); // L1 is 120KB and shd=8KB - else if (total_shmed > 8192 && total_shmed <= 16384) - m_L1D_config.set_assoc(0.875 * - max_assoc); // L1 is 112KB and shd=16KB - else if (total_shmed > 16384 && total_shmed <= 32768) - m_L1D_config.set_assoc(0.75 * max_assoc); // L1 is 96KB and - // shd=32KB - else if (total_shmed > 32768 && total_shmed <= 65536) - m_L1D_config.set_assoc(0.5 * max_assoc); // L1 is 64KB and shd=64KB - else if (total_shmed > 65536 && total_shmed <= gpgpu_shmem_size) - m_L1D_config.set_assoc(0.25 * max_assoc); // L1 is 32KB and - // shd=96KB - else - assert(0); - break; + std::vector shmem_list; + for (unsigned i = 0; i < strlen(gpgpu_shmem_option); i++) { + char option[4]; + int j = 0; + while (gpgpu_shmem_option[i] != ',' && i < strlen(gpgpu_shmem_option)) { + if (gpgpu_shmem_option[i] == ' ') { + // skip spaces + i++; + } else { + if (!isdigit(gpgpu_shmem_option[i])) { + // check for non digits, which should not be here + assert(0 && "invalid config: -gpgpu_shmem_option"); + } + option[j] = gpgpu_shmem_option[i]; + j++; + i++; } - default: - assert(0); } + // convert KB -> B + shmem_list.push_back((unsigned)atoi(option) * 1024); + } - printf("GPGPU-Sim: Reconfigure L1 cache to %uKB\n", - m_L1D_config.get_total_size_inKB()); + unsigned total_shmem = kernel_info->smem * result; + unsigned total_unified = gpgpu_unified_l1d_size * 1024; + std::sort(shmem_list.begin(), shmem_list.end()); + + assert(total_shmem >= 0 && total_shmem <= shmem_list.back()); + switch (adaptive_cache_config) { + case FIXED: + break; + case ADAPTIVE_CACHE: { + // For more info about adaptive cache, see + bool l1d_configured = false; + unsigned l1_defined = m_L1D_config.get_original_sz() / 1024; + unsigned max_assoc = m_L1D_config.get_original_assoc() * + gpgpu_unified_l1d_size / l1_defined; + + if (total_shmem == 0) { + m_L1D_config.set_assoc(max_assoc); + l1d_configured = true; + } else { + for (std::vector::iterator it = shmem_list.begin(); + it < shmem_list.end() - 1; it++) { + if (total_shmem > *it && total_shmem <= *(it + 1)) { + float l1_ratio = 1 - (float) *(it + 1) / total_unified; + m_L1D_config.set_assoc(max_assoc * l1_ratio); + l1d_configured = true; + break; + } + } + } + assert(l1d_configured && "no shared memory option found"); + break; + } + default: + assert(0); } + printf("GPGPU-Sim: Reconfigure L1 cache to %uKB\n", + m_L1D_config.get_total_size_inKB()); + k.cache_config_set = true; } -- cgit v1.3 From 4a762a933a054b5124fa46a12789ea98f5e2411d Mon Sep 17 00:00:00 2001 From: JRPAN <25518778+JRPan@users.noreply.github.com> Date: Wed, 19 May 2021 15:22:31 -0400 Subject: formatting again --- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 4 ++-- configs/tested-cfgs/SM7_QV100/gpgpusim.config | 8 ++------ configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +- src/gpgpu-sim/gpu-sim.cc | 2 +- src/gpgpu-sim/shader.cc | 1 + 5 files changed, 7 insertions(+), 10 deletions(-) (limited to 'src/gpgpu-sim/shader.cc') diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index e006085..d7573ab 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -100,6 +100,8 @@ # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo -gpgpu_adaptive_cache_config 0 +-gpgpu_shmem_option 0,8,16,32,64,100 +-gpgpu_unified_l1d_size 128 -gpgpu_l1_banks 4 -gpgpu_cache:dl1 S:1:128:512,L:L:m:N:L,A:512:8,16:0,32 -gpgpu_shmem_size 65536 @@ -110,8 +112,6 @@ -gpgpu_l1_latency 20 -gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 --gpgpu_shmem_option 0,8,16,32,64,100 --gpgpu_unified_l1d_size 128 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives us 3MB L2 cache -gpgpu_cache:dl2 S:64:128:16,L:B:m:L:P,A:192:4,32:0,32 diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index 043fce6..59c7f43 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -124,7 +124,7 @@ -gpgpu_l1_latency 20 -gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 --gpgpu_cache_write_ratio 25 +-gpgpu_l1_cache_write_ratio 25 -gpgpu_shmem_option 0,12,24,48,96 -gpgpu_unified_l1d_size 128 @@ -204,8 +204,4 @@ # tracing functionality #-trace_enabled 1 #-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - --gpgpu_cache_write_ratio 25 --gpgpu_shmem_option 0,12,24,48,96 --gpgpu_unified_l1d_size 128 \ No newline at end of file +#-trace_sampling_core 0 \ No newline at end of file diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 1f0c15f..3e080bc 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -125,7 +125,7 @@ -gpgpu_l1_latency 20 -gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 --gpgpu_cache_write_ratio 25 +-gpgpu_l1_cache_write_ratio 25 -gpgpu_shmem_option 0,12,24,48,96 -gpgpu_unified_l1d_size 128 diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index bd09cdb..a2aa929 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -249,7 +249,7 @@ void shader_core_config::reg_options(class OptionParser *opp) { " {::,:::,::, | none}", "none"); - option_parser_register(opp,"-gpgpu_cache_write_ratio",OPT_UINT32,&m_L1D_config.m_wr_percent,"L1D write ratio","0"); + option_parser_register(opp,"-gpgpu_l1_cache_write_ratio",OPT_UINT32,&m_L1D_config.m_wr_percent,"L1D write ratio","0"); option_parser_register(opp, "-gpgpu_l1_banks", OPT_UINT32, &m_L1D_config.l1_banks, "The number of L1 cache banks", "1"); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index b2adb4f..141c700 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3326,6 +3326,7 @@ unsigned int shader_core_config::max_cta(const kernel_info_t &k) const { // For more info about adaptive cache, see bool l1d_configured = false; unsigned l1_defined = m_L1D_config.get_original_sz() / 1024; + assert(gpgpu_unified_l1d_size % l1_defined == 0); unsigned max_assoc = m_L1D_config.get_original_assoc() * gpgpu_unified_l1d_size / l1_defined; -- cgit v1.3 From f27da224f3e468d600499a9d3619009ed9c70256 Mon Sep 17 00:00:00 2001 From: JRPAN <25518778+JRPan@users.noreply.github.com> Date: Wed, 19 May 2021 17:27:43 -0400 Subject: Use cache config multipilier when possible --- src/abstract_hardware_model.h | 1 - src/gpgpu-sim/gpu-cache.h | 28 +++++++++++++++------------- src/gpgpu-sim/gpu-sim.cc | 2 +- src/gpgpu-sim/shader.cc | 8 +++----- 4 files changed, 19 insertions(+), 20 deletions(-) (limited to 'src/gpgpu-sim/shader.cc') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index bd10a93..dbe138a 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -374,7 +374,6 @@ class core_config { unsigned mem_warp_parts; mutable unsigned gpgpu_shmem_size; char *gpgpu_shmem_option; - unsigned gpgpu_unified_l1d_size; unsigned gpgpu_shmem_sizeDefault; unsigned gpgpu_shmem_sizePrefL1; unsigned gpgpu_shmem_sizePrefShared; diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 0162b6c..87a6b13 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -512,6 +512,14 @@ class cache_config { exit_parse_error(); } + // set * assoc * cacheline size. Then convert Byte to KB + unsigned original_size = m_nset * m_assoc * m_line_sz / 1024; + if (m_unified_cache_size > 0) { + max_cache_multiplier = m_unified_cache_size / original_size; + } else { + max_cache_multiplier = MAX_DEFAULT_CACHE_SIZE_MULTIBLIER; + } + switch (ct) { case 'N': m_cache_type = NORMAL; @@ -588,7 +596,7 @@ class cache_config { // https://ieeexplore.ieee.org/document/8344474/ m_is_streaming = true; m_alloc_policy = ON_FILL; - m_mshr_entries = m_nset * m_assoc * MAX_DEFAULT_CACHE_SIZE_MULTIBLIER; + m_mshr_entries = m_nset * m_assoc * max_cache_multiplier; if (m_cache_type == SECTOR) m_mshr_entries *= SECTOR_CHUNCK_SIZE; m_mshr_max_merge = MAX_WARP_PER_SM; } @@ -616,7 +624,6 @@ class cache_config { m_atom_sz = (m_cache_type == SECTOR) ? SECTOR_SIZE : m_line_sz; m_sector_sz_log2 = LOGB2(SECTOR_SIZE); original_m_assoc = m_assoc; - original_sz = m_nset * original_m_assoc * m_line_sz; // For more details about difference between FETCH_ON_WRITE and WRITE @@ -706,19 +713,13 @@ class cache_config { } unsigned get_max_num_lines() const { assert(m_valid); - return MAX_DEFAULT_CACHE_SIZE_MULTIBLIER * m_nset * original_m_assoc; + // gpgpu_unified_cache_size is in KB while original_sz is in B + return max_cache_multiplier * m_nset * original_m_assoc; } unsigned get_max_assoc() const { assert(m_valid); - return MAX_DEFAULT_CACHE_SIZE_MULTIBLIER * original_m_assoc; - } - unsigned get_original_assoc() const { - assert(m_valid); - return original_m_assoc; - } - unsigned get_original_sz() const { - assert(m_valid); - return original_sz; + // gpgpu_unified_cache_size is in KB while original_sz is in B + return max_cache_multiplier * original_m_assoc; } void print(FILE *fp) const { fprintf(fp, "Size = %d B (%d Set x %d-way x %d byte line)\n", @@ -766,6 +767,7 @@ class cache_config { char *m_config_stringPrefShared; FuncCache cache_status; unsigned m_wr_percent; + unsigned m_unified_cache_size; write_allocate_policy_t get_write_allocate_policy() { return m_write_alloc_policy; } @@ -787,8 +789,8 @@ class cache_config { unsigned m_atom_sz; unsigned m_sector_sz_log2; unsigned original_m_assoc; - unsigned original_sz; bool m_is_streaming; + unsigned max_cache_multiplier; enum replacement_policy_t m_replacement_policy; // 'L' = LRU, 'F' = FIFO enum write_policy_t diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index a2aa929..df30047 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -331,7 +331,7 @@ void shader_core_config::reg_options(class OptionParser *opp) { opp, "-gpgpu_shmem_option", OPT_CSTR, &gpgpu_shmem_option, "Option list of shared memory sizes", "0"); option_parser_register( - opp, "-gpgpu_unified_l1d_size", OPT_UINT32, &gpgpu_unified_l1d_size, + opp, "-gpgpu_unified_l1d_size", OPT_UINT32, &m_L1D_config.m_unified_cache_size, "Size of unified data cache(L1D + shared memory) in KB", "0"); option_parser_register(opp, "-gpgpu_adaptive_cache_config", OPT_BOOL, &adaptive_cache_config, "adaptive_cache_config", "0"); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 141c700..3efef2b 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3315,7 +3315,8 @@ unsigned int shader_core_config::max_cta(const kernel_info_t &k) const { } unsigned total_shmem = kernel_info->smem * result; - unsigned total_unified = gpgpu_unified_l1d_size * 1024; + // Unified cache config is in KB. Converting to B + unsigned total_unified = m_L1D_config.m_unified_cache_size * 1024; std::sort(shmem_list.begin(), shmem_list.end()); assert(total_shmem >= 0 && total_shmem <= shmem_list.back()); @@ -3325,10 +3326,7 @@ unsigned int shader_core_config::max_cta(const kernel_info_t &k) const { case ADAPTIVE_CACHE: { // For more info about adaptive cache, see bool l1d_configured = false; - unsigned l1_defined = m_L1D_config.get_original_sz() / 1024; - assert(gpgpu_unified_l1d_size % l1_defined == 0); - unsigned max_assoc = m_L1D_config.get_original_assoc() * - gpgpu_unified_l1d_size / l1_defined; + unsigned max_assoc = m_L1D_config.get_max_assoc(); if (total_shmem == 0) { m_L1D_config.set_assoc(max_assoc); -- cgit v1.3