From b09eeed6aa36239f661d6452e996e3e5f8ef5984 Mon Sep 17 00:00:00 2001 From: Tayler Hetherington Date: Wed, 19 Sep 2012 14:51:45 -0800 Subject: Revision #2 of modifying the cache hierarchy. Separated the L1 and L2 cache access() implementations. Removed PRIVATE/SHARED cache scope configurations. Added WRITE_EVICT cache write policy. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14109] --- src/gpgpu-sim/shader.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gpgpu-sim/shader.cc') diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 7b65add..0dd8fd0 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1122,7 +1122,7 @@ ldst_unit::ldst_unit( mem_fetch_interface *icnt, m_L1C = new read_only_cache(L1C_name,m_config->m_L1C_config,m_sid,get_shader_constant_cache_id(),icnt,IN_L1C_MISS_QUEUE); m_L1D = NULL; if( !m_config->m_L1D_config.disabled() ) - m_L1D = new data_cache(L1D_name,m_config->m_L1D_config,m_sid,get_shader_normal_cache_id(),m_icnt,m_mf_allocator,IN_L1D_MISS_QUEUE); + m_L1D = new l1_cache(L1D_name,m_config->m_L1D_config,m_sid,get_shader_normal_cache_id(),m_icnt,m_mf_allocator,IN_L1D_MISS_QUEUE); m_mem_rc = NO_RC_FAIL; m_num_writeback_clients=5; // = shared memory, global/local (uncached), L1D, L1T, L1C m_writeback_arb = 0; -- cgit v1.3