From bb4cc3179dd36e882fb78732c9dfb99b1528b8d9 Mon Sep 17 00:00:00 2001 From: Wilson Fung Date: Wed, 17 Jul 2013 16:44:50 -0800 Subject: Redesigned the memory partition unit to support multiple L2 cache banks per partition. Each L2 cache banks has its own connection to the interconnection network to allow L2 bandwidth to scale without increase the number of memory parttiion units. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16613] --- src/gpgpu-sim/shader.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gpgpu-sim/shader.cc') diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 87e59ed..73a8a62 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3184,7 +3184,7 @@ void simt_core_cluster::icnt_inject_request_packet(class mem_fetch *mf) packet_size = mf->get_ctrl_size(); } m_stats->m_outgoing_traffic_stats->record_traffic(mf, packet_size); - unsigned destination = mf->get_tlx_addr().chip; + unsigned destination = mf->get_sub_partition_id(); mf->set_status(IN_ICNT_TO_MEM,gpu_sim_cycle+gpu_tot_sim_cycle); if (!mf->get_is_write() && !mf->isatomic()) ::icnt_push(m_cluster_id, m_config->mem2device(destination), (void*)mf, mf->get_ctrl_size() ); -- cgit v1.3