From b64d38562079a7d4720c15c9f6309912f4090795 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Fri, 8 Oct 2010 13:05:25 -0800 Subject: 1. modify shader_core_ctx::execute_pipe() to model instruction throughput correctly (off-by-one error) 2. adding code to dump_pipeline to display reason for memory stage stalling 3. removing dead code resulting from prior changes correlation vs. GT200 is 0.95 (need to add back modeling of memory writebacks, shared memory latency) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7831] --- src/gpgpu-sim/shader.h | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'src/gpgpu-sim/shader.h') diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index cdbaf37..a9e27b8 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1130,8 +1130,6 @@ private: opndcoll_rfu_t m_operand_collector; mshr_shader_unit *m_mshr_unit; shader_queues_t m_memory_queue; - fifo_pipeline > *m_thd_commit_queue; - std::multiset m_fixeddelay_queue; // fetch int m_last_warp_fetched; @@ -1143,12 +1141,7 @@ private: cache_t *m_L1C; // constant cache bool m_shader_memory_new_instruction_processed; - int m_pending_mem_access; // number of memory access to be serviced (use for W0 classification) - - // used in writeback - int *m_pl_tid; - insn_latency_info *m_mshr_lat_info; - insn_latency_info *m_pl_lat_info; + enum mem_stage_stall_type m_mem_rc; }; void init_mshr_pool(); -- cgit v1.3