From 3321626d5e858df8e2154bf4e7a1bacda76658e7 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Thu, 13 Nov 2014 17:16:44 -0500 Subject: ADD: support concurrent kernels on one shader --- src/gpgpu-sim/shader.h | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) (limited to 'src/gpgpu-sim/shader.h') diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 38d09e9..fcbc8aa 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1327,6 +1327,9 @@ struct shader_core_config : public core_config int simt_core_sim_order; unsigned mem2device(unsigned memid) const { return memid + n_simt_clusters; } + + //Jin: concurrent kernel on sm + bool gpgpu_concurrent_kernel_sm; }; struct shader_core_stats_pod { @@ -1574,6 +1577,7 @@ public: void cycle(); void reinit(unsigned start_thread, unsigned end_thread, bool reset_not_completed ); void issue_block2core( class kernel_info_t &kernel ); + void cache_flush(); void accept_fetch_response( mem_fetch *mf ); void accept_ldst_unit_response( class mem_fetch * mf ); @@ -1582,7 +1586,7 @@ public: { assert(k); m_kernel=k; - k->inc_running(); +// k->inc_running(); printf("GPGPU-Sim uArch: Shader %d bind to kernel %u \'%s\'\n", m_sid, m_kernel->get_uid(), m_kernel->name().c_str() ); } @@ -1749,7 +1753,7 @@ public: virtual void checkExecutionStatusAndUpdate(warp_inst_t &inst, unsigned t, unsigned tid); address_type next_pc( int tid ) const; void fetch(); - void register_cta_thread_exit( unsigned cta_num ); + void register_cta_thread_exit( unsigned cta_num, kernel_info_t * kernel ); void decode(); @@ -1831,6 +1835,20 @@ public: // is that the dynamic_warp_id is a running number unique to every warp // run on this shader, where the warp_id is the static warp slot. unsigned m_dynamic_warp_id; + + //Jin: concurrent kernels on a sm +public: + bool can_issue_1block(kernel_info_t & kernel); + bool occupy_shader_resource_1block(kernel_info_t & kernel, bool occupy); + void release_shader_resource_1block(kernel_info_t & kernel); + int find_available_hwtid(unsigned int cta_size); +private: + unsigned int m_occupied_n_threads; + unsigned int m_occupied_shmem; + unsigned int m_occupied_regs; + unsigned int m_occupied_ctas; + + }; class simt_core_cluster { @@ -1851,6 +1869,7 @@ public: bool icnt_injection_buffer_full(unsigned size, bool write); void icnt_inject_request_packet(class mem_fetch *mf); + // for perfect memory interface bool response_queue_full() { return ( m_response_fifo.size() >= m_config->n_simt_ejection_buffer_size ); -- cgit v1.3 From 8ef2e4eb13093c59190439800fdd0cc552a3779e Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Fri, 14 Nov 2014 18:45:46 -0500 Subject: ADD: add cdp latency --- src/abstract_hardware_model.h | 8 ++++++-- src/cuda-sim/cuda-sim.cc | 21 ++++++++++++++++----- src/cuda-sim/ptx_ir.cc | 10 ++++++---- src/gpgpu-sim/shader.cc | 26 ++++++++++++++++++++++++++ src/gpgpu-sim/shader.h | 13 +++++++++++++ 5 files changed, 67 insertions(+), 11 deletions(-) (limited to 'src/gpgpu-sim/shader.h') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 3a268ad..45334b6 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -867,7 +867,7 @@ public: m_mem_accesses_created=false; m_cache_hit=false; m_is_printf=false; - m_is_cdp = false; + m_is_cdp = 0; } virtual ~warp_inst_t(){ } @@ -1020,7 +1020,6 @@ protected: unsigned cycles; // used for implementing initiation interval delay bool m_isatomic; bool m_is_printf; - bool m_is_cdp; unsigned m_warp_id; unsigned m_dynamic_warp_id; const core_config *m_config; @@ -1041,6 +1040,11 @@ protected: std::list m_accessq; static unsigned sm_next_uid; + + //Jin: cdp support +public: + int m_is_cdp; + }; void move_warp( warp_inst_t *&dst, warp_inst_t *&src ); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 276cb9d..9ecd92b 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -64,6 +64,8 @@ unsigned gpgpu_param_num_shaders = 0; char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp; char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp; +char *cdp_latency_str; +unsigned cdp_latency[4]; void ptx_opcocde_latency_options (option_parser_t opp) { option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, @@ -90,6 +92,11 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Opcode initiation intervals for double precision floating points " "Default 8,8,8,8,130", "8,8,8,8,130"); + option_parser_register(opp, "-cdp_latency", OPT_CSTR, &cdp_latency_str, + "CDP API latency " + "Default 1,7200,19320,1680", + "1,7200,19320,1680"); } static address_type get_converge_point(address_type pc); @@ -609,6 +616,8 @@ void ptx_instruction::set_opcode_and_latency() sscanf(opcode_initiation_dp, "%u,%u,%u,%u,%u", &dp_init[0],&dp_init[1],&dp_init[2], &dp_init[3],&dp_init[4]); + sscanf(cdp_latency_str, "%u,%u,%u,%u", + &cdp_latency[0],&cdp_latency[1],&cdp_latency[2], &cdp_latency[3]); if(!m_operands.empty()){ std::vector::iterator it; @@ -639,19 +648,21 @@ void ptx_instruction::set_opcode_and_latency() case MEMBAR_OP: op = MEMORY_BARRIER_OP; break; case CALL_OP: { - if(m_is_printf || m_is_cdp) + if(m_is_printf || m_is_cdp) { op = ALU_OP; + } else op = CALL_OPS; break; } case CALLP_OP: { - if(m_is_printf || m_is_cdp) + if(m_is_printf || m_is_cdp) { op = ALU_OP; - else - op = CALL_OPS; - break; + } + else + op = CALL_OPS; + break; } case RET_OP: case RETP_OP: op = RET_OPS;break; case ADD_OP: case ADDP_OP: case ADDC_OP: case SUB_OP: case SUBC_OP: diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 176eb14..4931213 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1241,10 +1241,12 @@ ptx_instruction::ptx_instruction( int opcode, if (fname =="vprintf"){ m_is_printf = true; } - if (fname == "cudaGetParameterBufferV2" - || fname == "cudaLaunchDeviceV2" - || fname == "cudaStreamCreateWithFlags") - m_is_cdp = true; + if(fname == "cudaGetParameterBufferV2") + m_is_cdp = 1; + if(fname == "cudaStreamCreateWithFlags") + m_is_cdp = 2; + if(fname == "cudaLaunchDeviceV2") + m_is_cdp = 3; } } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index cd38cb7..e85c4a8 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -841,6 +841,13 @@ void scheduler_unit::cycle() unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp; while( !warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue) ) { const warp_inst_t *pI = warp(warp_id).ibuffer_next_inst(); + //Jin: handle cdp latency; + if(pI->m_is_cdp && warp(warp_id).m_cdp_latency > 0) { + assert(warp(warp_id).m_cdp_dummy); + warp(warp_id).m_cdp_latency--; + break; + } + bool valid = warp(warp_id).ibuffer_next_valid(); bool warp_inst_issued = false; unsigned pc,rpc; @@ -875,6 +882,25 @@ void scheduler_unit::cycle() bool sp_pipe_avail = m_sp_out->has_free(); bool sfu_pipe_avail = m_sfu_out->has_free(); if( sp_pipe_avail && (pI->op != SFU_OP) ) { + + //Jin: special for CDP api + if(pI->m_is_cdp && !warp(warp_id).m_cdp_dummy) { + assert(warp(warp_id).m_cdp_latency == 0); + + extern unsigned cdp_latency[3]; + if(pI->m_is_cdp != 3) + warp(warp_id).m_cdp_latency = cdp_latency[pI->m_is_cdp - 1]; + else //cudaLaunchDeviceV2 + warp(warp_id).m_cdp_latency = cdp_latency[pI->m_is_cdp - 1] + + cdp_latency[pI->m_is_cdp] * active_mask.count(); + warp(warp_id).m_cdp_dummy = true; + break; + } + else if(pI->m_is_cdp && warp(warp_id).m_cdp_dummy) { + assert(warp(warp_id).m_cdp_latency == 0); + warp(warp_id).m_cdp_dummy = false; + } + // always prefer SP pipe for operations that can use both SP and SFU pipelines m_shader->issue_warp(*m_sp_out,pI,active_mask,warp_id); issued++; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index fcbc8aa..882868e 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -108,6 +108,10 @@ public: m_last_fetch=0; m_next=0; m_inst_at_barrier=NULL; + + //Jin: cdp support + m_cdp_latency = 0; + m_cdp_dummy = false; } void init( address_type start_pc, unsigned cta_id, @@ -124,6 +128,10 @@ public: n_completed -= active.count(); // active threads are not yet completed m_active_threads = active; m_done_exit=false; + + //Jin: cdp support + m_cdp_latency = 0; + m_cdp_dummy = false; } bool functional_done() const; @@ -260,6 +268,11 @@ private: unsigned m_stores_outstanding; // number of store requests sent but not yet acknowledged unsigned m_inst_in_pipeline; + + //Jin: cdp support +public: + unsigned int m_cdp_latency; + bool m_cdp_dummy; }; -- cgit v1.3 From 9c0384c1626205b4a9ed97f998b3d4d8e7758198 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Fri, 14 Nov 2014 22:11:52 -0500 Subject: BUG: concurrent kernels on same SM may occupy warps from running CTAs --- src/gpgpu-sim/gpu-sim.cc | 27 +++++++++++++++++++++------ src/gpgpu-sim/shader.cc | 7 +++++-- src/gpgpu-sim/shader.h | 8 +++++--- 3 files changed, 31 insertions(+), 11 deletions(-) (limited to 'src/gpgpu-sim/shader.h') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 10c4ccf..81c9c9a 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1092,7 +1092,7 @@ bool shader_core_ctx::can_issue_1block(kernel_info_t & kernel) { return occupy_shader_resource_1block(kernel, false); } -int shader_core_ctx::find_available_hwtid(unsigned int cta_size) { +int shader_core_ctx::find_available_hwtid(unsigned int cta_size, bool occupy) { unsigned int step; for(step = 0; step < m_config->n_thread_per_shader; @@ -1101,7 +1101,7 @@ int shader_core_ctx::find_available_hwtid(unsigned int cta_size) { unsigned int hw_tid; for(hw_tid = step; hw_tid < step + cta_size; hw_tid++) { - if(m_active_threads.test(hw_tid)) + if(m_occupied_hwtid.test(hw_tid)) break; } if(hw_tid == step + cta_size) //consecutive non-active @@ -1109,8 +1109,14 @@ int shader_core_ctx::find_available_hwtid(unsigned int cta_size) { } if(step >= m_config->n_thread_per_shader) //didn't find return -1; - else + else { + if(occupy) { + for(unsigned hw_tid = step; hw_tid < step + cta_size; + hw_tid++) + m_occupied_hwtid.set(hw_tid); + } return step; + } } bool shader_core_ctx::occupy_shader_resource_1block(kernel_info_t & k, bool occupy) { @@ -1124,7 +1130,7 @@ bool shader_core_ctx::occupy_shader_resource_1block(kernel_info_t & k, bool occu if(m_occupied_n_threads + padded_cta_size > m_config->n_thread_per_shader) return false; - if(find_available_hwtid(padded_cta_size) == -1) + if(find_available_hwtid(padded_cta_size, false) == -1) return false; const struct gpgpu_ptx_sim_kernel_info *kernel_info = ptx_sim_kernel_info(kernel); @@ -1152,7 +1158,7 @@ bool shader_core_ctx::occupy_shader_resource_1block(kernel_info_t & k, bool occu return true; } -void shader_core_ctx::release_shader_resource_1block(kernel_info_t & k) { +void shader_core_ctx::release_shader_resource_1block(unsigned hw_ctaid, kernel_info_t & k) { unsigned threads_per_cta = k.threads_per_cta(); const class function_info *kernel = k.entry(); unsigned int padded_cta_size = threads_per_cta; @@ -1163,6 +1169,13 @@ void shader_core_ctx::release_shader_resource_1block(kernel_info_t & k) { assert(m_occupied_n_threads >= padded_cta_size); m_occupied_n_threads -= padded_cta_size; + int start_thread = m_occupied_cta_to_hwtid[hw_ctaid]; + + for(unsigned hwtid = start_thread; hwtid < start_thread + padded_cta_size; + hwtid++) + m_occupied_hwtid.reset(hwtid); + m_occupied_cta_to_hwtid.erase(hw_ctaid); + const struct gpgpu_ptx_sim_kernel_info *kernel_info = ptx_sim_kernel_info(kernel); assert(m_occupied_shmem >= (unsigned int)kernel_info->smem); @@ -1211,9 +1224,11 @@ void shader_core_ctx::issue_block2core( kernel_info_t &kernel ) int padded_cta_size = cta_size; if (cta_size%m_config->warp_size) padded_cta_size = ((cta_size/m_config->warp_size)+1)*(m_config->warp_size); - unsigned int start_thread = find_available_hwtid(padded_cta_size); + unsigned int start_thread = find_available_hwtid(padded_cta_size, true); assert((int)start_thread != -1); unsigned int end_thread = start_thread + cta_size; + assert(m_occupied_cta_to_hwtid.find(free_cta_hw_id) == m_occupied_cta_to_hwtid.end()); + m_occupied_cta_to_hwtid[free_cta_hw_id]= start_thread; // unsigned start_thread = free_cta_hw_id * padded_cta_size; // unsigned end_thread = start_thread + cta_size; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 8ce2146..b9caf18 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -302,6 +302,8 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_occupied_shmem = 0; m_occupied_regs = 0; m_occupied_ctas = 0; + m_occupied_hwtid.reset(); + m_occupied_cta_to_hwtid.clear(); } void shader_core_ctx::reinit(unsigned start_thread, unsigned end_thread, bool reset_not_completed ) @@ -315,6 +317,8 @@ void shader_core_ctx::reinit(unsigned start_thread, unsigned end_thread, bool re m_occupied_shmem = 0; m_occupied_regs = 0; m_occupied_ctas = 0; + m_occupied_hwtid.reset(); + m_occupied_cta_to_hwtid.clear(); } for (unsigned i = start_thread; im_is_cdp - 1] + cdp_latency[pI->m_is_cdp] * active_mask.count(); - printf("set latency %d\n", warp(warp_id).m_cdp_latency); warp(warp_id).m_cdp_dummy = true; break; } @@ -1980,7 +1983,7 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num, kernel_info_t } //Jin: for concurrent kernels on sm - release_shader_resource_1block(*kernel); + release_shader_resource_1block(cta_num, *kernel); kernel->dec_running(); if( !m_gpu->kernel_more_cta_left(kernel) ) { if( !kernel->running() ) { diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 882868e..bdd8dbe 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1766,7 +1766,7 @@ public: virtual void checkExecutionStatusAndUpdate(warp_inst_t &inst, unsigned t, unsigned tid); address_type next_pc( int tid ) const; void fetch(); - void register_cta_thread_exit( unsigned cta_num, kernel_info_t * kernel ); + void register_cta_thread_exit(unsigned cta_num, kernel_info_t * kernel ); void decode(); @@ -1853,13 +1853,15 @@ public: public: bool can_issue_1block(kernel_info_t & kernel); bool occupy_shader_resource_1block(kernel_info_t & kernel, bool occupy); - void release_shader_resource_1block(kernel_info_t & kernel); - int find_available_hwtid(unsigned int cta_size); + void release_shader_resource_1block(unsigned hw_ctaid, kernel_info_t & kernel); + int find_available_hwtid(unsigned int cta_size, bool occupy); private: unsigned int m_occupied_n_threads; unsigned int m_occupied_shmem; unsigned int m_occupied_regs; unsigned int m_occupied_ctas; + std::bitset m_occupied_hwtid; + std::map m_occupied_cta_to_hwtid; }; -- cgit v1.3