From 6e06c2e1de8c51a88845b7f35cea219dca7456f2 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sun, 28 Nov 2010 20:48:33 -0800 Subject: enabling L2 data cache... it is write through, write evict like L1. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8154] --- src/gpgpu-sim/visualizer.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/gpgpu-sim/visualizer.cc') diff --git a/src/gpgpu-sim/visualizer.cc b/src/gpgpu-sim/visualizer.cc index c2b1d16..1c32692 100644 --- a/src/gpgpu-sim/visualizer.cc +++ b/src/gpgpu-sim/visualizer.cc @@ -394,9 +394,9 @@ void time_vector_print_interval2gzfile(gzFile outfile) { #include "../gpgpu-sim/mem_fetch.h" void time_vector_update(unsigned int uid,int slot ,long int cycle,int type) { - if ( (type == RD_REQ) || (type == REPLY_DATA) ) { + if ( (type == READ_REQUEST) || (type == READ_REPLY) ) { g_my_time_vector->update_ld( uid, slot,cycle); - } else if ( type == WR_REQ ) { + } else if ( (type == WRITE_REQUEST) || (type == WRITE_ACK) ) { g_my_time_vector->update_st( uid, slot,cycle); } else { abort(); @@ -405,9 +405,9 @@ void time_vector_update(unsigned int uid,int slot ,long int cycle,int type) { void check_time_vector_update(unsigned int uid,int slot ,long int latency,int type) { - if ( (type == RD_REQ) || (type == REPLY_DATA) ) { + if ( (type == READ_REQUEST) || (type == READ_REPLY) ) { g_my_time_vector->check_ld_update( uid, slot, latency ); - } else if ( type == WR_REQ ) { + } else if ( (type == WRITE_REQUEST) || (type == WRITE_ACK) ) { g_my_time_vector->check_st_update( uid, slot, latency ); } else { abort(); -- cgit v1.3