From 87e4da5fc6086c3d0a661af1929255a8cbd728d7 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Mon, 18 Oct 2010 02:43:17 -0800 Subject: Re-designed cache model: - read only cache model with integrated mshrs (no L1D, yet); new cache interface should be easily extendable to support texture cache with latency fifo and separate tag/data arrays, though this is not yet added (currently tags and data arrays are not decoupled for texture) - new partition model using the above removes all old MSHRs, L1D etc... passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7875] --- src/gpgpu-sim/visualizer.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gpgpu-sim/visualizer.h') diff --git a/src/gpgpu-sim/visualizer.h b/src/gpgpu-sim/visualizer.h index 0d9424a..8c74d53 100644 --- a/src/gpgpu-sim/visualizer.h +++ b/src/gpgpu-sim/visualizer.h @@ -67,7 +67,7 @@ void visualizer_options(class OptionParser *opp); void visualizer_printstat( class shader_core_ctx **sc, unsigned n_shader, class dram_t **dram, unsigned n_mem ); -void time_vector_create(int ld_size,int st_size); +void time_vector_create(int size); void time_vector_print(void); void time_vector_update(unsigned int uid,int slot ,long int cycle,int type); void check_time_vector_update(unsigned int uid,int slot ,long int latency,int type); -- cgit v1.3