From e700b1816492bb811e5aa12d1b1b0ec778e04235 Mon Sep 17 00:00:00 2001 From: Ahmad Alawneh Date: Tue, 6 Jun 2023 22:58:29 -0400 Subject: fix types, change int to unsigned int --- src/gpgpu-sim/gpu-sim.cc | 14 +++++++------- src/gpgpu-sim/shader.cc | 6 +++--- src/gpgpu-sim/shader.h | 14 +++++++------- 3 files changed, 17 insertions(+), 17 deletions(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 5a68f13..ea50fa0 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -586,26 +586,26 @@ void shader_core_config::reg_options(class OptionParser *opp) { "ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_" "INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE", "1,1,1,1,1,1,1,1,1,1,1,1,1"); - option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_INT32, + option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_UINT32, &gpgpu_tensor_core_avail, "Tensor Core Available (default=0)", "0"); - option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32, + option_parser_register(opp, "-gpgpu_num_sp_units", OPT_UINT32, &gpgpu_num_sp_units, "Number of SP units (default=1)", "1"); - option_parser_register(opp, "-gpgpu_num_dp_units", OPT_INT32, + option_parser_register(opp, "-gpgpu_num_dp_units", OPT_UINT32, &gpgpu_num_dp_units, "Number of DP units (default=0)", "0"); - option_parser_register(opp, "-gpgpu_num_int_units", OPT_INT32, + option_parser_register(opp, "-gpgpu_num_int_units", OPT_UINT32, &gpgpu_num_int_units, "Number of INT units (default=0)", "0"); - option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_INT32, + option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_UINT32, &gpgpu_num_sfu_units, "Number of SF units (default=1)", "1"); - option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32, + option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_UINT32, &gpgpu_num_tensor_core_units, "Number of tensor_core units (default=1)", "0"); option_parser_register( - opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units, + opp, "-gpgpu_num_mem_units", OPT_UINT32, &gpgpu_num_mem_units, "Number if ldst units (default=1) WARNING: not hooked up to anything", "1"); option_parser_register( diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 4ae0f62..fdc7f77 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -107,7 +107,7 @@ void shader_core_ctx::create_front_pipeline() { m_pipeline_reg.push_back( register_set(m_config->pipe_widths[j], pipeline_stage_name_decode[j])); } - for (int j = 0; j < m_config->m_specialized_unit.size(); j++) { + for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) { m_pipeline_reg.push_back( register_set(m_config->m_specialized_unit[j].id_oc_spec_reg_width, m_config->m_specialized_unit[j].name)); @@ -115,7 +115,7 @@ void shader_core_ctx::create_front_pipeline() { m_specilized_dispatch_reg.push_back( &m_pipeline_reg[m_pipeline_reg.size() - 1]); } - for (int j = 0; j < m_config->m_specialized_unit.size(); j++) { + for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) { m_pipeline_reg.push_back( register_set(m_config->m_specialized_unit[j].oc_ex_spec_reg_width, m_config->m_specialized_unit[j].name)); @@ -140,7 +140,7 @@ void shader_core_ctx::create_front_pipeline() { if (m_config->gpgpu_num_int_units > 0) assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_INT].get_size()); - for (int j = 0; j < m_config->m_specialized_unit.size(); j++) { + for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) { if (m_config->m_specialized_unit[j].num_units > 0) assert(m_config->gpgpu_num_sched_per_core == m_config->m_specialized_unit[j].id_oc_spec_reg_width); diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index deea1c9..c486d13 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1622,13 +1622,13 @@ class shader_core_config : public core_config { unsigned int gpgpu_operand_collector_num_out_ports_gen; unsigned int gpgpu_operand_collector_num_out_ports_int; - int gpgpu_num_sp_units; - int gpgpu_tensor_core_avail; - int gpgpu_num_dp_units; - int gpgpu_num_sfu_units; - int gpgpu_num_tensor_core_units; - int gpgpu_num_mem_units; - int gpgpu_num_int_units; + unsigned int gpgpu_num_sp_units; + unsigned int gpgpu_tensor_core_avail; + unsigned int gpgpu_num_dp_units; + unsigned int gpgpu_num_sfu_units; + unsigned int gpgpu_num_tensor_core_units; + unsigned int gpgpu_num_mem_units; + unsigned int gpgpu_num_int_units; // Shader core resources unsigned gpgpu_shader_registers; -- cgit v1.3 From ccf6662429efcfcf28d1050455163e41553a31f6 Mon Sep 17 00:00:00 2001 From: Ahmad Alawneh Date: Wed, 7 Jun 2023 00:05:06 -0400 Subject: fix more Wsign warnings --- src/gpgpu-sim/addrdec.cc | 2 +- src/gpgpu-sim/power_interface.cc | 10 +++++----- src/gpgpu-sim/shader.cc | 10 +++++----- src/gpgpu-sim/shader.h | 4 ++-- src/intersim2/networks/anynet.cpp | 2 +- src/intersim2/vc.cpp | 2 +- 6 files changed, 15 insertions(+), 15 deletions(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc index 19714ec..f4f83f9 100644 --- a/src/gpgpu-sim/addrdec.cc +++ b/src/gpgpu-sim/addrdec.cc @@ -519,7 +519,7 @@ void linear_to_raw_address_translation::sweep_test() const { h->second, raw_addr); abort(); } else { - assert((int)tlx.chip < m_n_channel); + assert(tlx.chip < m_n_channel); // ensure that partition_address() returns the concatenated address if ((ADDR_CHIP_S != -1 and raw_addr >= (1ULL << ADDR_CHIP_S)) or (ADDR_CHIP_S == -1 and raw_addr >= (1ULL << addrdec_mklow[CHIP]))) { diff --git a/src/gpgpu-sim/power_interface.cc b/src/gpgpu-sim/power_interface.cc index 470f2f9..45a09bc 100644 --- a/src/gpgpu-sim/power_interface.cc +++ b/src/gpgpu-sim/power_interface.cc @@ -269,7 +269,7 @@ void calculate_hw_mcpat(const gpgpu_sim_config &config, if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_L1_WM])) l1_write_misses = power_stats->get_l1d_write_misses(1) - power_stats->l1w_misses_kernel; - if(aggregate_power_stats){ + if(aggregate_power_stats){ power_stats->tot_inst_execution += power_stats->get_total_inst(1); power_stats->tot_int_inst_execution += power_stats->get_total_int_inst(1); power_stats->tot_fp_inst_execution += power_stats->get_total_fp_inst(1); @@ -281,16 +281,16 @@ void calculate_hw_mcpat(const gpgpu_sim_config &config, l1_read_hits + l1_read_misses, l1_write_hits + l1_write_misses, power_stats->commited_inst_execution); - } - else{ - wrapper->set_inst_power( + } + else{ + wrapper->set_inst_power( shdr_config->gpgpu_clock_gated_lanes, cycle, //TODO: core.[0] cycles counts don't matter, remove this cycle, power_stats->get_total_inst(1), power_stats->get_total_int_inst(1), power_stats->get_total_fp_inst(1), l1_read_hits + l1_read_misses, l1_write_hits + l1_write_misses, power_stats->get_committed_inst(1)); - } + } // Single RF for both int and fp ops -- activity factor set to 0 for Accelwattch HW and Accelwattch Hybrid because no HW Perf Stats for register files wrapper->set_regfile_power(power_stats->get_regfile_reads(1), diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index fdc7f77..f756aec 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1645,7 +1645,7 @@ void swl_scheduler::order_warps() { } void shader_core_ctx::read_operands() { - for (int i = 0; i < m_config->reg_file_port_throughput; ++i) + for (unsigned int i = 0; i < m_config->reg_file_port_throughput; ++i) m_operand_collector.step(); } @@ -1948,7 +1948,7 @@ mem_stage_stall_type ldst_unit::process_memory_access_queue_l1cache( if (inst.accessq_empty()) return result; if (m_config->m_L1D_config.l1_latency > 0) { - for (int j = 0; j < m_config->m_L1D_config.l1_banks; + for (unsigned int j = 0; j < m_config->m_L1D_config.l1_banks; j++) { // We can handle at max l1_banks reqs per cycle if (inst.accessq_empty()) return result; @@ -2001,7 +2001,7 @@ mem_stage_stall_type ldst_unit::process_memory_access_queue_l1cache( } void ldst_unit::L1_latency_queue_cycle() { - for (int j = 0; j < m_config->m_L1D_config.l1_banks; j++) { + for (unsigned int j = 0; j < m_config->m_L1D_config.l1_banks; j++) { if ((l1_latency_queue[j][0]) != NULL) { mem_fetch *mf_next = l1_latency_queue[j][0]; std::list events; @@ -2328,7 +2328,7 @@ sp_unit::sp_unit(register_set *result_port, const shader_core_config *config, specialized_unit::specialized_unit(register_set *result_port, const shader_core_config *config, - shader_core_ctx *core, unsigned supported_op, + shader_core_ctx *core, int supported_op, char *unit_name, unsigned latency, unsigned issue_reg_id) : pipelined_simd_unit(result_port, config, latency, core, issue_reg_id) { @@ -3501,7 +3501,7 @@ void shader_core_ctx::cycle() { execute(); read_operands(); issue(); - for (int i = 0; i < m_config->inst_fetch_throughput; ++i) { + for (unsigned int i = 0; i < m_config->inst_fetch_throughput; ++i) { decode(); fetch(); } diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index c486d13..fd4fc1f 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1284,7 +1284,7 @@ class sp_unit : public pipelined_simd_unit { class specialized_unit : public pipelined_simd_unit { public: specialized_unit(register_set *result_port, const shader_core_config *config, - shader_core_ctx *core, unsigned supported_op, + shader_core_ctx *core, int supported_op, char *unit_name, unsigned latency, unsigned issue_reg_id); virtual bool can_issue(const warp_inst_t &inst) const { if (inst.op != m_supported_op) { @@ -1297,7 +1297,7 @@ class specialized_unit : public pipelined_simd_unit { bool is_issue_partitioned() { return true; } private: - unsigned m_supported_op; + int m_supported_op; }; class simt_core_cluster; diff --git a/src/intersim2/networks/anynet.cpp b/src/intersim2/networks/anynet.cpp index 4db1dfb..d7c6f22 100644 --- a/src/intersim2/networks/anynet.cpp +++ b/src/intersim2/networks/anynet.cpp @@ -491,7 +491,7 @@ void AnyNet::readFile(){ } sort(node_check.begin(), node_check.end()); for(size_t i = 0; i= 0) { - if(f->pid != _expected_pid) { + if((long long int)f->pid != _expected_pid) { ostringstream err; err << "Received flit " << f->id << " with unexpected packet ID: " << f->pid << " (expected: " << _expected_pid << ")"; -- cgit v1.3