From b2def455d573f66fbc38dabda4adbc3a56225910 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Sun, 9 Feb 2020 20:39:22 -0500 Subject: adding kepler sass, skip-first-kernel and update config file --- src/gpgpu-sim/gpu-sim.cc | 3 +++ src/gpgpu-sim/gpu-sim.h | 4 +++- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 7f9985e..4e38f67 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -573,6 +573,9 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) option_parser_register(opp, "-trace_driven_mode", OPT_BOOL, &trace_driven_mode, "Turn on trace_driven_mode", "0"); + option_parser_register(opp, "-trace_skip_first_kernel", OPT_BOOL, + &trace_skip_first_kernel, "skip first intiliztion kernel in trace mode", + "0"); option_parser_register(opp, "-trace", OPT_CSTR, &g_traces_filename, "traces kernel file" "traces kernel file directory", diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 1ac4fdb..abc905e 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -348,7 +348,8 @@ public: size_t sync_depth_limit() const {return runtime_sync_depth_limit; } size_t pending_launch_count_limit() const {return runtime_pending_launch_count_limit;} - unsigned is_trace_driven_mode() const { return trace_driven_mode; } + bool is_trace_driven_mode() const { return trace_driven_mode; } + bool is_skip_first_kernel() const { return trace_skip_first_kernel; } char* get_traces_filename() const { return g_traces_filename; } bool flush_l1() const { return gpgpu_flush_l1_cache; } @@ -408,6 +409,7 @@ private: //trace driven mode options bool trace_driven_mode; + bool trace_skip_first_kernel; char *g_traces_filename; friend class gpgpu_sim; -- cgit v1.3 From 1d3ccd32e70c6a6c524abbe8ff0ac450481290d4 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Mon, 10 Feb 2020 21:28:09 -0500 Subject: removing assertion in random hashing --- src/gpgpu-sim/addrdec.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc index 670bd61..c34cb32 100644 --- a/src/gpgpu-sim/addrdec.cc +++ b/src/gpgpu-sim/addrdec.cc @@ -221,7 +221,7 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_ { //This is an unrealistic hashing using software hashtable //we generate a random set for each memory address and save the value in a big hashtable for future reuse - assert(!gap); + //assert(!gap); new_addr_type chip_address = (addr>>(ADDR_CHIP_S-log2sub_partition)); tr1_hash_map::const_iterator got = address_random_interleaving.find (chip_address); if ( got == address_random_interleaving.end() ) { -- cgit v1.3 From 5221ed98c5a7f0ceec3eb96216f4449635a74b22 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Thu, 13 Feb 2020 12:32:39 -0500 Subject: fixing pascal --- src/gpgpu-sim/shader.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 23050d3..7fc31f3 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -106,7 +106,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, } if(m_config->sub_core_model) { //in subcore model, each scheduler should has its own issue register, so num scheduler = reg width - assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_SP].get_size() ); + //assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_SP].get_size() ); assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_SFU].get_size() ); assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_MEM].get_size() ); if(m_config->gpgpu_tensor_core_avail) -- cgit v1.3 From 024cb02ecadc58c401b9cbeb558774c6ba7415aa Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Thu, 26 Mar 2020 14:11:10 -0400 Subject: fixing core fetch bw --- src/gpgpu-sim/shader.cc | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 7fc31f3..e206d9c 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -889,7 +889,7 @@ void shader_core_ctx::fetch() assert( status == RESERVATION_FAIL ); delete mf; } - break; + //break; } } } @@ -1067,7 +1067,18 @@ void scheduler_unit::cycle() exec_unit_type_t previous_issued_inst_exec_type = exec_unit_type_t::NONE; unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp; bool diff_exec_units = m_shader->m_config->gpgpu_dual_issue_diff_exec_units; //In tis mode, we only allow dual issue to diff execution units (as in Maxwell and Pascal) - + + if(warp(warp_id).ibuffer_empty()) + SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) fails as ibuffer_empty\n", + (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id() ); + + if(warp(warp_id).waiting()) + SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) fails as waiting for barrier\n", + (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id() ); + + if((*iter)->get_warp_id() ==2 ) + printf(" Hello! I am here! \n "); + while( !warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue) ) { const warp_inst_t *pI = warp(warp_id).ibuffer_next_inst(); //Jin: handle cdp latency; @@ -1120,13 +1131,13 @@ void scheduler_unit::cycle() } } else { - bool sp_pipe_avail = m_sp_out->has_free(m_shader->m_config->sub_core_model, m_id); - bool sfu_pipe_avail = m_sfu_out->has_free(m_shader->m_config->sub_core_model, m_id); - bool tensor_core_pipe_avail = m_tensor_core_out->has_free(m_shader->m_config->sub_core_model, m_id); - bool dp_pipe_avail = m_dp_out->has_free(m_shader->m_config->sub_core_model, m_id); - bool int_pipe_avail = m_int_out->has_free(m_shader->m_config->sub_core_model, m_id); + bool sp_pipe_avail = (m_shader->m_config->gpgpu_num_sp_units > 0) && m_sp_out->has_free(m_shader->m_config->sub_core_model, m_id); + bool sfu_pipe_avail = (m_shader->m_config->gpgpu_num_sfu_units > 0) && m_sfu_out->has_free(m_shader->m_config->sub_core_model, m_id); + bool tensor_core_pipe_avail = (m_shader->m_config->gpgpu_num_tensor_core_units > 0) && m_tensor_core_out->has_free(m_shader->m_config->sub_core_model, m_id); + bool dp_pipe_avail = (m_shader->m_config->gpgpu_num_dp_units > 0) && m_dp_out->has_free(m_shader->m_config->sub_core_model, m_id); + bool int_pipe_avail = (m_shader->m_config->gpgpu_num_int_units > 0) && m_int_out->has_free(m_shader->m_config->sub_core_model, m_id); - //This code need to be refactored + //This code needs to be refactored if(pI->op != TENSOR_CORE_OP && pI->op != SFU_OP && pI->op != DP_OP) { bool execute_on_SP = false; @@ -1196,7 +1207,7 @@ void scheduler_unit::cycle() previous_issued_inst_exec_type = exec_unit_type_t::SFU; } } - else if ( (pI->op == TENSOR_CORE_OP) && !(diff_exec_units && previous_issued_inst_exec_type == exec_unit_type_t::SP) ) { + else if ( (pI->op == TENSOR_CORE_OP) && !(diff_exec_units && previous_issued_inst_exec_type == exec_unit_type_t::TENSOR) ) { if( tensor_core_pipe_avail ) { m_shader->issue_warp(*m_tensor_core_out,pI,active_mask,warp_id,m_id); issued++; -- cgit v1.3 From 38a5c4d70539cdacf1ce20394027d9b705ff9c76 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Thu, 26 Mar 2020 18:18:17 -0400 Subject: increase inst fetch thoughput --- src/gpgpu-sim/shader.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index e206d9c..a2850d0 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -106,7 +106,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, } if(m_config->sub_core_model) { //in subcore model, each scheduler should has its own issue register, so num scheduler = reg width - //assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_SP].get_size() ); + assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_SP].get_size() ); assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_SFU].get_size() ); assert(m_config->gpgpu_num_sched_per_core == m_pipeline_reg[ID_OC_MEM].get_size() ); if(m_config->gpgpu_tensor_core_avail) @@ -889,7 +889,7 @@ void shader_core_ctx::fetch() assert( status == RESERVATION_FAIL ); delete mf; } - //break; + break; } } } @@ -1074,10 +1074,7 @@ void scheduler_unit::cycle() if(warp(warp_id).waiting()) SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) fails as waiting for barrier\n", - (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id() ); - - if((*iter)->get_warp_id() ==2 ) - printf(" Hello! I am here! \n "); + (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id() ); while( !warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue) ) { const warp_inst_t *pI = warp(warp_id).ibuffer_next_inst(); @@ -3178,8 +3175,11 @@ void shader_core_ctx::cycle() execute(); read_operands(); issue(); + for(int i=0; i<8; ++i) { decode(); fetch(); + printf("Hello! \n"); + } } // Flushes all content of the cache to memory -- cgit v1.3 From ed97d2a5b0096fb8afa4bc83fe2df515b2a2399c Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Tue, 31 Mar 2020 13:00:34 -0400 Subject: adding inst fetch throughput --- src/gpgpu-sim/gpu-sim.cc | 4 +++- src/gpgpu-sim/shader.cc | 9 +++++---- src/gpgpu-sim/shader.h | 1 + 3 files changed, 9 insertions(+), 5 deletions(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 4e38f67..4ef9a7d 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -470,7 +470,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-perfect_inst_const_cache", OPT_BOOL, &perfect_inst_const_cache, "perfect inst and const cache mode, so all inst and const hits in the cache(default = disabled)", "0"); - + option_parser_register(opp, "-inst_fetch_throughput", OPT_INT32, &inst_fetch_throughput, + "the number of fetched intruction per warp each cycle", + "1"); } void gpgpu_sim_config::reg_options(option_parser_t opp) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index a2850d0..297f3bc 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3175,10 +3175,9 @@ void shader_core_ctx::cycle() execute(); read_operands(); issue(); - for(int i=0; i<8; ++i) { - decode(); - fetch(); - printf("Hello! \n"); + for(int i=0; i< m_config->inst_fetch_throughput; ++i) { + decode(); + fetch(); } } @@ -3235,6 +3234,7 @@ std::list opndcoll_rfu_t::arbiter_t::allocate_reads() ///// wavefront allocator from booksim... ---> // Loop through diagonals of request matrix + printf("####\n"); for ( int p = 0; p < _square; ++p ) { output = ( _pri + p ) % _square; @@ -3250,6 +3250,7 @@ std::list opndcoll_rfu_t::arbiter_t::allocate_reads() // Grant! _inmatch[input] = output; _outmatch[output] = input; + printf("Register File: granting banks %d to OC % \n", input, output); } output = ( output + 1 ) % _square; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index d41c220..43c448b 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1524,6 +1524,7 @@ class shader_core_config : public core_config bool gpgpu_concurrent_kernel_sm; bool perfect_inst_const_cache; + unsigned inst_fetch_throughput; }; -- cgit v1.3 From eb618e6bbe0bac135ba800a5880f18040f35acf8 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Tue, 31 Mar 2020 13:33:42 -0400 Subject: adding some RF stats --- src/gpgpu-sim/shader.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 297f3bc..afd63e8 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3250,7 +3250,7 @@ std::list opndcoll_rfu_t::arbiter_t::allocate_reads() // Grant! _inmatch[input] = output; _outmatch[output] = input; - printf("Register File: granting banks %d to OC % \n", input, output); + printf("Register File: granting bank %d to OC %d, schedid %d, warpid %d, Regid %d\n", input, output, (m_queue[output].front()).get_sid(), (m_queue[output].front()).get_wid(), (m_queue[output].front()).get_reg()); } output = ( output + 1 ) % _square; -- cgit v1.3 From cc5d6636df7388e44c5203e5580a2aa50c0fd6b1 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Tue, 31 Mar 2020 16:38:14 -0400 Subject: fixing the RF assertion --- src/gpgpu-sim/shader.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index afd63e8..d9f7b94 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3237,7 +3237,7 @@ std::list opndcoll_rfu_t::arbiter_t::allocate_reads() printf("####\n"); for ( int p = 0; p < _square; ++p ) { - output = ( _pri + p ) % _square; + output = ( _pri + p ) % _outputs; // Step through the current diagonal for ( input = 0; input < _inputs; ++input ) { @@ -3250,15 +3250,15 @@ std::list opndcoll_rfu_t::arbiter_t::allocate_reads() // Grant! _inmatch[input] = output; _outmatch[output] = input; - printf("Register File: granting bank %d to OC %d, schedid %d, warpid %d, Regid %d\n", input, output, (m_queue[output].front()).get_sid(), (m_queue[output].front()).get_wid(), (m_queue[output].front()).get_reg()); + printf("Register File: granting bank %d to OC %d, schedid %d, warpid %d, Regid %d\n", input, output, (m_queue[input].front()).get_sid(), (m_queue[input].front()).get_wid(), (m_queue[input].front()).get_reg()); } - output = ( output + 1 ) % _square; + output = ( output + 1 ) % _outputs; } } // Round-robin the priority diagonal - _pri = ( _pri + 1 ) % _square; + _pri = ( _pri + 1 ) % _outputs; /// <--- end code from booksim -- cgit v1.3 From 3633eacca183608fe1a666212ba468b787c063a5 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Tue, 31 Mar 2020 20:43:41 -0400 Subject: adding new comments --- src/gpgpu-sim/gpu-sim.cc | 3 +++ src/gpgpu-sim/shader.cc | 13 +++++++------ src/gpgpu-sim/shader.h | 1 + 3 files changed, 11 insertions(+), 6 deletions(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 4ef9a7d..94ea6d2 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -473,6 +473,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-inst_fetch_throughput", OPT_INT32, &inst_fetch_throughput, "the number of fetched intruction per warp each cycle", "1"); + option_parser_register(opp, "-gpgpu_reg_file_port_throughput", OPT_INT32, ®_file_port_throughput, + "the number ports of the register file", + "1"); } void gpgpu_sim_config::reg_options(option_parser_t opp) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index d9f7b94..ed0c25e 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -384,12 +384,12 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_fu.push_back(new dp_unit( &m_pipeline_reg[EX_WB], m_config, this )); m_dispatch_port.push_back(ID_OC_DP); m_issue_port.push_back(OC_EX_DP); - } + } for (int k = 0; k < m_config->gpgpu_num_int_units; k++) { m_fu.push_back(new int_unit( &m_pipeline_reg[EX_WB], m_config, this )); m_dispatch_port.push_back(ID_OC_INT); m_issue_port.push_back(OC_EX_INT); - } + } for (int k = 0; k < m_config->gpgpu_num_sfu_units; k++) { m_fu.push_back(new sfu( &m_pipeline_reg[EX_WB], m_config, this )); @@ -2413,7 +2413,8 @@ void ldst_unit::issue( register_set ®_set ) void ldst_unit::cycle() { writeback(); - m_operand_collector->step(); + for(int i=0; i< m_config->reg_file_port_throughput; ++i) + m_operand_collector->step(); for( unsigned stage=0; (stage+1)empty() && !m_pipeline_reg[stage+1]->empty() ) move_warp(m_pipeline_reg[stage], m_pipeline_reg[stage+1]); @@ -3234,7 +3235,7 @@ std::list opndcoll_rfu_t::arbiter_t::allocate_reads() ///// wavefront allocator from booksim... ---> // Loop through diagonals of request matrix - printf("####\n"); + // printf("####\n"); for ( int p = 0; p < _square; ++p ) { output = ( _pri + p ) % _outputs; @@ -3245,12 +3246,12 @@ std::list opndcoll_rfu_t::arbiter_t::allocate_reads() assert( output < _outputs ); if ( ( output < _outputs ) && ( _inmatch[input] == -1 ) && - ( _outmatch[output] == -1 ) && + //( _outmatch[output] == -1 ) && //allow OC to read multiple reg banks at the same cycle ( _request[input][output]/*.label != -1*/ ) ) { // Grant! _inmatch[input] = output; _outmatch[output] = input; - printf("Register File: granting bank %d to OC %d, schedid %d, warpid %d, Regid %d\n", input, output, (m_queue[input].front()).get_sid(), (m_queue[input].front()).get_wid(), (m_queue[input].front()).get_reg()); + // printf("Register File: granting bank %d to OC %d, schedid %d, warpid %d, Regid %d\n", input, output, (m_queue[input].front()).get_sid(), (m_queue[input].front()).get_wid(), (m_queue[input].front()).get_reg()); } output = ( output + 1 ) % _outputs; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 43c448b..665e3a5 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1525,6 +1525,7 @@ class shader_core_config : public core_config bool perfect_inst_const_cache; unsigned inst_fetch_throughput; + unsigned reg_file_port_throughput; }; -- cgit v1.3 From bd647361e2b8eb2d72f0055df851fcdee53e94cc Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Tue, 31 Mar 2020 20:54:44 -0400 Subject: fixing the tensor unit failing --- src/gpgpu-sim/gpu-sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 94ea6d2..e5b9c9d 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -453,7 +453,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "1"); option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32, &gpgpu_num_tensor_core_units, "Number of tensor_core units (default=1)", - "1"); + "0"); option_parser_register(opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units, "Number if ldst units (default=1) WARNING: not hooked up to anything", "1"); -- cgit v1.3 From 52204ff08a9c9a21a99fee3f976d2a419c014fec Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Mon, 18 May 2020 21:49:34 -0400 Subject: fixing some failing apps --- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 6 +++--- configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config | 4 ++-- src/gpgpu-sim/gpu-sim.cc | 3 ++- src/gpgpu-sim/shader.cc | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) (limited to 'src/gpgpu-sim') diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index e8329dd..b89971e 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -33,9 +33,9 @@ # volta clock domains #-gpgpu_clock_domains ::: --gpgpu_clock_domains 1365.0:1365.0:1365.0:7000.0 +-gpgpu_clock_domains 1365.0:1365.0:1365.0:3500.0 # boost mode -# -gpgpu_clock_domains 1680.0:1680.0:1680.0:7000.0 +# -gpgpu_clock_domains 1680.0:1680.0:1680.0:3500.0 # shader core pipeline config -gpgpu_shader_registers 65536 @@ -156,7 +156,7 @@ -gpgpu_n_mem_per_ctrlr 1 -gpgpu_dram_buswidth 2 -gpgpu_dram_burst_length 16 --dram_data_command_freq_ratio 2 # GDDR6 is configured as DDR in Turing +-dram_data_command_freq_ratio 4 -gpgpu_mem_address_mask 1 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS diff --git a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config index 0255f76..0df3eec 100644 --- a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config @@ -74,8 +74,8 @@ -ptx_opcode_initiation_dp 4,4,4,4,130 -ptx_opcode_latency_sfu 100 -ptx_opcode_initiation_sfu 8 --ptx_opcode_latency_tesnor 6 --ptx_opcode_initiation_tensor 2 +-ptx_opcode_latency_tesnor 8 +-ptx_opcode_initiation_tensor 4 # Volta has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index e5b9c9d..cd5fa56 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1828,7 +1828,8 @@ void shader_core_ctx::dump_warp_state( FILE *fout ) const void gpgpu_sim::perf_memcpy_to_gpu( size_t dst_start_addr, size_t count ) { if (m_memory_config->m_perf_sim_memcpy) { - assert (dst_start_addr % 32 == 0); + //if(!m_config.trace_driven_mode) //in trace-driven mode, CUDA runtime can start nre data structure at any position + // assert (dst_start_addr % 32 == 0); for ( unsigned counter = 0; counter < count; counter += 32 ) { const unsigned wr_addr = dst_start_addr + counter; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index ed0c25e..65ec113 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3091,7 +3091,7 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const case VOLTA: { //For Volta, we assign the remaining shared memory to L1 cache //For more info about adaptive cache, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x - assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared + //assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared //To Do: make it flexible and not tuned to 9KB share memory unsigned max_assoc = m_L1D_config.get_max_assoc(); -- cgit v1.3