From 826a0dc10ca939af1f2c24d0d2e63eb2b33cb731 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sun, 24 Oct 2010 13:05:48 -0800 Subject: 1. updates to .gdbinit file 2. update texture to bypass ROP-delay queue... correlation now 0.9592 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7912] --- src/gpgpu-sim/gpu-sim.cc | 4 ++-- src/gpgpu-sim/gpu-sim.h | 1 - src/gpgpu-sim/l2cache.cc | 33 ++++++++++++++++++++------------- src/gpgpu-sim/l2cache.h | 2 +- src/gpgpu-sim/shader.cc | 19 ++++++++----------- src/gpgpu-sim/shader.h | 6 +++--- 6 files changed, 34 insertions(+), 31 deletions(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 8c1be87..dbae72c 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -749,7 +749,7 @@ void gpgpu_sim::cycle() // L2 operations follow L2 clock domain if (clock_mask & L2) { for (unsigned i=0;im_n_mem;i++) - m_memory_partition_unit[i]->cache_cycle(); + m_memory_partition_unit[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle); } if (clock_mask & ICNT) { @@ -885,7 +885,7 @@ void gpgpu_sim::dump_pipeline( int mask, int s, int m ) const if(s != -1) { i = s; } - if(mask&1) m_cluster[sid_to_cluster(i)]->display_pipeline(i,stdout,1,mask & 0x2E); + if(mask&1) m_cluster[m_shader_config->sid_to_cluster(i)]->display_pipeline(i,stdout,1,mask & 0x2E); if(s != -1) { break; } diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 903eb3c..54b32d0 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -286,7 +286,6 @@ private: void print_shader_cycle_distro( FILE *fout ) const; void gpgpu_debug(); - unsigned sid_to_cluster( unsigned sid ) const; ///// data ///// diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index fa55d0b..14f1f12 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -120,7 +120,7 @@ memory_partition_unit::~memory_partition_unit() delete m_L2interface; } -void memory_partition_unit::cache_cycle() +void memory_partition_unit::cache_cycle( unsigned cycle ) { // L2 fill responses if ( m_L2cache->access_ready() && !m_L2_icnt_queue->full() ) { @@ -172,6 +172,14 @@ void memory_partition_unit::cache_cycle() m_icnt_L2_queue->pop(); } } + + // ROP delay queue + if( !m_rop.empty() && (cycle >= m_rop.front().ready_cycle) && !m_icnt_L2_queue->full() ) { + mem_fetch* mf = m_rop.front().req; + m_rop.pop(); + m_icnt_L2_queue->push(mf); + mf->set_status(IN_PARTITION_ICNT_TO_L2_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); + } } bool memory_partition_unit::full() const @@ -231,18 +239,17 @@ void memory_partition_unit::push( mem_fetch* req, unsigned long long cycle ) { if (req) { m_request_tracker.insert(req); - rop_delay_t r; - r.req = req; - r.ready_cycle = cycle + 115; // Add 115*4=460 delay cycles - m_rop.push(r); - req->set_status(IN_PARTITION_ROP_DELAY,gpu_sim_cycle+gpu_tot_sim_cycle); - } - if ( !m_rop.empty() && (cycle >= m_rop.front().ready_cycle) ) { - mem_fetch* mf = m_rop.front().req; - m_rop.pop(); - m_stats->memlatstat_icnt2mem_pop(mf); - m_icnt_L2_queue->push(mf); - mf->set_status(IN_PARTITION_ICNT_TO_L2_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); + m_stats->memlatstat_icnt2mem_pop(req); + if( req->istexture() ) { + m_icnt_L2_queue->push(req); + req->set_status(IN_PARTITION_ICNT_TO_L2_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); + } else { + rop_delay_t r; + r.req = req; + r.ready_cycle = cycle + 115; // Add 115*4=460 delay cycles + m_rop.push(r); + req->set_status(IN_PARTITION_ROP_DELAY,gpu_sim_cycle+gpu_tot_sim_cycle); + } } } diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index b80f384..b7ab49e 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -82,7 +82,7 @@ public: bool busy() const; - void cache_cycle(); + void cache_cycle( unsigned cycle ); void dram_cycle(); bool full() const; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index f723b78..692eace 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -309,14 +309,9 @@ void pdom_warp_ctx_t::pdom_update_warp_mask() assert(scheduled_warp->m_stack_top < m_warp_size * 2); } -unsigned gpgpu_sim::sid_to_cluster( unsigned sid ) const -{ - return sid / m_shader_config->n_simt_cores_per_cluster; -} - void gpgpu_sim::get_pdom_stack_top_info( unsigned sid, unsigned tid, unsigned *pc, unsigned *rpc ) { - unsigned cluster_id = sid_to_cluster(sid); + unsigned cluster_id = m_shader_config->sid_to_cluster(sid); m_cluster[cluster_id]->get_pdom_stack_top_info(sid,tid,pc,rpc); } @@ -2002,8 +1997,10 @@ simt_core_cluster::simt_core_cluster( class gpgpu_sim *gpu, m_gpu = gpu; m_stats = stats; m_core = new shader_core_ctx*[ config->n_simt_cores_per_cluster ]; - for( unsigned i=0; i < config->n_simt_cores_per_cluster; i++ ) - m_core[i] = new shader_core_ctx(gpu,this,cid_to_sid(i),m_cluster_id,config,mem_config,stats); + for( unsigned i=0; i < config->n_simt_cores_per_cluster; i++ ) { + unsigned sid = m_config->cid_to_sid(i,m_cluster_id); + m_core[i] = new shader_core_ctx(gpu,this,sid,m_cluster_id,config,mem_config,stats); + } } void simt_core_cluster::core_cycle() @@ -2095,7 +2092,7 @@ void simt_core_cluster::icnt_cycle() { if( !m_response_fifo.empty() ) { mem_fetch *mf = m_response_fifo.front(); - unsigned cid = sid_to_cid(mf->get_sid()); + unsigned cid = m_config->sid_to_cid(mf->get_sid()); if( mf->get_access_type() == INST_ACC_R ) { // instruction fetch response if( !m_core[cid]->fetch_unit_response_buffer_full() ) { @@ -2124,11 +2121,11 @@ void simt_core_cluster::icnt_cycle() void simt_core_cluster::get_pdom_stack_top_info( unsigned sid, unsigned tid, unsigned *pc, unsigned *rpc ) const { - unsigned cid = sid_to_cid(sid); + unsigned cid = m_config->sid_to_cid(sid); m_core[cid]->get_pdom_stack_top_info(tid,pc,rpc); } void simt_core_cluster::display_pipeline( unsigned sid, FILE *fout, int print_mem, int mask ) { - m_core[sid_to_cid(sid)]->display_pipeline(fout,print_mem,mask); + m_core[m_config->sid_to_cid(sid)]->display_pipeline(fout,print_mem,mask); } diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index dd3d89e..52a7e35 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -936,6 +936,9 @@ struct shader_core_config : public core_config void reg_options(class OptionParser * opp ); unsigned max_cta( const kernel_info_t &k ) const; unsigned num_shader() const { return n_simt_clusters*n_simt_cores_per_cluster; } + unsigned sid_to_cluster( unsigned sid ) const { return sid / n_simt_cores_per_cluster; } + unsigned sid_to_cid( unsigned sid ) const { return sid % n_simt_cores_per_cluster; } + unsigned cid_to_sid( unsigned cid, unsigned cluster_id ) const { return cluster_id*n_simt_cores_per_cluster + cid; } // data char *gpgpu_shader_core_pipeline_opt; @@ -1183,9 +1186,6 @@ public: void display_pipeline( unsigned sid, FILE *fout, int print_mem, int mask ); private: - unsigned sid_to_cid( unsigned sid ) const { return sid % m_config->n_simt_cores_per_cluster; } - unsigned cid_to_sid( unsigned cid ) const { return m_cluster_id*m_config->n_simt_cores_per_cluster + cid; } - unsigned m_cluster_id; gpgpu_sim *m_gpu; const shader_core_config *m_config; -- cgit v1.3