From 0e46a261dfeba9c19d1637f46277986d7eb1b9d8 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Tue, 9 Oct 2018 17:12:57 -0400 Subject: adding adaptive volta cache config --- src/gpgpu-sim/gpu-cache.cc | 9 ++++----- src/gpgpu-sim/gpu-cache.h | 31 +++++++++++++++++++++++++++---- src/gpgpu-sim/gpu-sim.cc | 3 +++ src/gpgpu-sim/shader.cc | 29 +++++++++++++++++++++++++++++ src/gpgpu-sim/shader.h | 2 ++ 5 files changed, 65 insertions(+), 9 deletions(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index a11853a..8ae4702 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -29,7 +29,6 @@ #include "stat-tool.h" #include -#define MAX_DEFAULT_CACHE_SIZE_MULTIBLIER 4 // used to allocate memory that is large enough to adapt the changes in cache size across kernels const char * cache_request_status_str(enum cache_request_status status) @@ -165,7 +164,7 @@ unsigned l2_cache_config::set_index(new_addr_type addr) const{ tag_array::~tag_array() { - unsigned cache_lines_num = MAX_DEFAULT_CACHE_SIZE_MULTIBLIER*m_config.get_num_lines(); + unsigned cache_lines_num = m_config.get_max_num_lines(); for(unsigned i=0; iis_modified_line()) { for(unsigned j=0; j < SECTOR_CHUNCK_SIZE; j++) m_lines[i]->set_status(INVALID, mem_access_sector_mask_t().set(j)) ; @@ -396,7 +395,7 @@ void tag_array::flush() void tag_array::invalidate() { - for (unsigned i=0; i < m_config.get_num_lines(); i++) + for (unsigned i=0; i < m_config.get_max_num_lines(); i++) for(unsigned j=0; j < SECTOR_CHUNCK_SIZE; j++) m_lines[i]->set_status(INVALID, mem_access_sector_mask_t().set(j)) ; } diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 4ed382c..9174d7f 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -38,6 +38,8 @@ #include "addrdec.h" #include +#define MAX_DEFAULT_CACHE_SIZE_MULTIBLIER 4 + enum cache_block_state { INVALID=0, RESERVED, @@ -557,15 +559,15 @@ public: } if(m_alloc_policy == STREAMING) { //For streaming cache, we set the alloc policy to be on-fill to remove all line_alloc_fail stalls - //we set the MSHRs to be equal to the cache line. This is possible by moving TAG to be shared between cache line and MSHR enrty (i.e. for each cache line, there is an MSHR rntey associated with it) - // This is the easiest think we can think about to model (mimics) L1 streaming cache in Pascal and Volta + //we set the MSHRs to be equal to max allocated cache lines. This is possible by moving TAG to be shared between cache line and MSHR enrty (i.e. for each cache line, there is an MSHR rntey associated with it) + //This is the easiest think we can think about to model (mimic) L1 streaming cache in Pascal and Volta //Based on our microbenchmakrs, MSHRs entries have been increasing substantially in Pascal and Volta //For more information about streaming cache, see: // http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf // https://ieeexplore.ieee.org/document/8344474/ m_alloc_policy = ON_FILL; - m_mshr_entries = m_nset*m_assoc; + m_mshr_entries = m_nset*m_assoc*MAX_DEFAULT_CACHE_SIZE_MULTIBLIER; if(m_cache_type == SECTOR) m_mshr_entries *= SECTOR_CHUNCK_SIZE; m_mshr_max_merge = MAX_WARP_PER_SM; @@ -581,6 +583,7 @@ public: m_nset_log2 = LOGB2(m_nset); m_valid = true; m_atom_sz = (m_cache_type == SECTOR)? SECTOR_SIZE : m_line_sz; + original_m_assoc = m_assoc; //For more details about difference between FETCH_ON_WRITE and WRITE VALIDAE policies //Read: Jouppi, Norman P. "Cache write policies and performance". ISCA 93. @@ -646,7 +649,11 @@ public: assert( m_valid ); return m_nset * m_assoc; } - + unsigned get_max_num_lines() const + { + assert( m_valid ); + return MAX_DEFAULT_CACHE_SIZE_MULTIBLIER * m_nset * original_m_assoc; + } void print( FILE *fp ) const { fprintf( fp, "Size = %d B (%d Set x %d-way x %d byte line)\n", @@ -687,6 +694,21 @@ public: { return m_mshr_type; } + void set_assoc(unsigned n) + { + //set new assoc. L1 cache dynamically resized in Volta + m_assoc = n; + } + unsigned get_nset() const + { + assert( m_valid ); + return m_nset; + } + unsigned get_total_size_inKB() const + { + assert( m_valid ); + return (m_assoc*m_nset*m_line_sz)/1024; + } FuncCache get_cache_status() {return cache_status;} char *m_config_string; char *m_config_stringPrefL1; @@ -708,6 +730,7 @@ protected: unsigned m_nset_log2; unsigned m_assoc; unsigned m_atom_sz; + unsigned original_m_assoc; enum replacement_policy_t m_replacement_policy; // 'L' = LRU, 'F' = FIFO enum write_policy_t m_write_policy; // 'T' = write through, 'B' = write back, 'R' = read only diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 08d4525..080cbac 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -307,6 +307,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size, "Size of shared memory per shader core (default 16kB)", "16384"); + option_parser_register(opp, "-adpative_volta_cache_config", OPT_BOOL, &adpative_volta_cache_config, + "adpative_volta_cache_config", + "0"); option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_sizeDefault, "Size of shared memory per shader core (default 16kB)", "16384"); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 0e2e1c2..2cc8a2e 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -2744,6 +2744,35 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const abort(); } + if(adpative_volta_cache_config && !k.volta_cache_config_set) { + //For Volta, we assign the remaining shared memory to L1 cache + //For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x + unsigned total_shmed = kernel_info->smem * result; + assert(total_shmed >=0 && total_shmed <= gpgpu_shmem_size); + assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared + assert(m_L1D_config.get_nset() == 4); //Volta L1 has four sets + if(total_shmed < gpgpu_shmem_size){ + if(total_shmed == 0) + m_L1D_config.set_assoc(256); //L1 is 128KB ans shd=0 + else if(total_shmed > 0 && total_shmed <= 8192) + m_L1D_config.set_assoc(240); //L1 is 120KB ans shd=8KB + else if(total_shmed > 8192 && total_shmed <= 16384) + m_L1D_config.set_assoc(224); //L1 is 112KB ans shd=16KB + else if(total_shmed > 16384 && total_shmed <= 32768) + m_L1D_config.set_assoc(192); //L1 is 96KB ans shd=32KB + else if(total_shmed > 32768 && total_shmed <= 65536) + m_L1D_config.set_assoc(128); //L1 is 64KB ans shd=64KB + else if(total_shmed > 65536 && total_shmed <= gpgpu_shmem_size) + m_L1D_config.set_assoc(64); //L1 is 32KB and shd=96KB + else + assert(0); + + printf ("GPGPU-Sim: Reconfigure L1 cache in Volta Archi to %uKB\n", m_L1D_config.get_total_size_inKB()); + } + + k.volta_cache_config_set = true; + } + return result; } diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index e07096e..92b4159 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1409,6 +1409,8 @@ struct shader_core_config : public core_config //Jin: concurrent kernel on sm bool gpgpu_concurrent_kernel_sm; + + bool adpative_volta_cache_config; }; struct shader_core_stats_pod { -- cgit v1.3 From d78eab6fdc4eb9ab9e0a86088a16872c2c6f9755 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 11 Oct 2018 12:55:10 -0400 Subject: improving the performance of cache flushing --- src/gpgpu-sim/gpu-cache.cc | 16 ++++++++++++++-- src/gpgpu-sim/gpu-cache.h | 2 ++ 2 files changed, 16 insertions(+), 2 deletions(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 8ae4702..fdcbdaf 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -222,6 +222,7 @@ void tag_array::init( int core_id, int type_id ) m_prev_snapshot_pending_hit = 0; m_core_id = core_id; m_type_id = type_id; + is_used = false; } @@ -316,6 +317,7 @@ enum cache_request_status tag_array::access( new_addr_type addr, unsigned time, enum cache_request_status tag_array::access( new_addr_type addr, unsigned time, unsigned &idx, bool &wb, evicted_block_info &evicted, mem_fetch* mf ) { m_access++; + is_used = true; shader_cache_access_log(m_core_id, m_type_id, 0); // log accesses to cache enum cache_request_status status = probe(addr,idx,mf); switch (status) { @@ -386,18 +388,28 @@ void tag_array::fill( unsigned index, unsigned time, mem_fetch* mf) //TODO: we need write back the flushed data to the upper level void tag_array::flush() { - for (unsigned i=0; i < m_config.get_max_num_lines(); i++) + if(!is_used) + return; + + for (unsigned i=0; i < m_config.get_num_lines(); i++) if(m_lines[i]->is_modified_line()) { for(unsigned j=0; j < SECTOR_CHUNCK_SIZE; j++) m_lines[i]->set_status(INVALID, mem_access_sector_mask_t().set(j)) ; } + + is_used = false; } void tag_array::invalidate() { - for (unsigned i=0; i < m_config.get_max_num_lines(); i++) + if(!is_used) + return; + + for (unsigned i=0; i < m_config.get_num_lines(); i++) for(unsigned j=0; j < SECTOR_CHUNCK_SIZE; j++) m_lines[i]->set_status(INVALID, mem_access_sector_mask_t().set(j)) ; + + is_used = false; } float tag_array::windowed_miss_rate( ) const diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 9174d7f..cd98945 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -839,6 +839,8 @@ protected: int m_core_id; // which shader core is using this int m_type_id; // what kind of cache is this (normal, texture, constant) + + bool is_used; //a flag if the whole cache has ever been accessed before }; class mshr_table { -- cgit v1.3