From 9ac6dbe8e9453c8f4ab8965e83a945146891d5be Mon Sep 17 00:00:00 2001 From: Inderpreet Singh Date: Wed, 3 Aug 2011 18:09:10 -0800 Subject: Added read to precharge constraint - negligible effect to DRAM efficiency. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9929] --- src/gpgpu-sim/dram.cc | 6 ++++-- src/gpgpu-sim/dram.h | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index b09033f..104ec66 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -264,6 +264,7 @@ void dram_t::cycle() bk[j]->mrq->txbytes += m_config->BL * m_config->busW * m_config->gpu_n_mem_per_ctrlr; //16 bytes CCDc = m_config->tCCD; RTWc = m_config->tRTW; + bk[j]->RTPc = m_config->BL/2; issued = true; n_rd++; bwutil+= m_config->BL/2; @@ -341,7 +342,7 @@ void dram_t::cycle() if ( (!issued) && (bk[j]->curr_row != bk[j]->mrq->row) && (bk[j]->state == BANK_ACTIVE) && - (!bk[j]->RASc && !bk[j]->WTPc) ) { + (!bk[j]->RASc && !bk[j]->WTPc && !bk[j]->RTPc) ) { // make the bank idle again bk[j]->state = BANK_IDLE; bk[j]->RPc = m_config->tRP; @@ -385,7 +386,8 @@ void dram_t::cycle() DEC2ZERO(bk[j]->RCc); DEC2ZERO(bk[j]->RPc); DEC2ZERO(bk[j]->RCDWRc); - DEC2ZERO(bk[j]->WTPc); + DEC2ZERO(bk[j]->WTPc); + DEC2ZERO(bk[j]->RTPc); } #ifdef DRAM_VISUALIZE diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index 6a28058..96b912b 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -65,7 +65,8 @@ struct bank_t unsigned int RASc; unsigned int RPc; unsigned int RCc; - unsigned int WTPc; // write to precharge + unsigned int WTPc; // write to precharge + unsigned int RTPc; // read to precharge unsigned char rw; //is the bank reading or writing? unsigned char state; //is the bank active or idle? -- cgit v1.3