From 9ce235efd70782eba687da0f3163ff0f3f2840ef Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sun, 24 Oct 2010 09:56:14 -0800 Subject: add back per shader icount tracking for visualizer [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7910] --- src/gpgpu-sim/gpu-sim.cc | 7 +- src/gpgpu-sim/gpu-sim.h | 1 - src/gpgpu-sim/mem_latency_stat.cc | 1 - src/gpgpu-sim/shader.cc | 82 +++------- src/gpgpu-sim/shader.h | 328 ++++++++++++++++++-------------------- 5 files changed, 187 insertions(+), 232 deletions(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index e31ab67..8c1be87 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -336,7 +336,6 @@ gpgpu_sim::gpgpu_sim( const gpgpu_sim_config &config ) gpu_sim_insn = 0; gpu_tot_sim_insn = 0; gpu_tot_issued_cta = 0; - gpu_tot_completed_thread = 0; gpu_deadlock = false; m_cluster = new simt_core_cluster*[m_shader_config->n_simt_clusters]; @@ -489,7 +488,6 @@ unsigned int gpgpu_sim::run_gpu_sim() m_memory_stats->memlatstat_lat_pw(m_config.num_shader(),m_shader_config->n_thread_per_shader,m_shader_config->warp_size); gpu_tot_sim_cycle += gpu_sim_cycle; gpu_tot_sim_insn += gpu_sim_insn; - gpu_tot_completed_thread += m_shader_stats->get_gpu_completed_thread(); ptx_file_line_stats_write_file(); @@ -545,7 +543,6 @@ void gpgpu_sim::gpu_print_stat() const printf("gpu_tot_sim_cycle = %lld\n", gpu_tot_sim_cycle); printf("gpu_tot_sim_insn = %lld\n", gpu_tot_sim_insn); printf("gpu_tot_ipc = %12.4f\n", (float)gpu_tot_sim_insn / gpu_tot_sim_cycle); - printf("gpu_tot_completed_thread = %lld\n", gpu_tot_completed_thread); printf("gpu_tot_issued_cta = %lld\n", gpu_tot_issued_cta); // performance counter for stalls due to congestion. @@ -666,14 +663,14 @@ void shader_core_ctx::issue_block2core( kernel_info_t &kernel ) // now that we know which warps are used in this CTA, we can allocate // resources for use in CTA-wide barrier operations - allocate_barrier( free_cta_hw_id, warps ); + m_barriers.allocate_barrier(free_cta_hw_id,warps); // initialize the SIMT stacks and fetch hardware init_warps( free_cta_hw_id, start_thread, end_thread); m_n_active_cta++; shader_CTA_count_log(m_sid, 1); - printf("GPGPU-Sim uArch: core:%d, cta:%u initialized @(%lld,%lld)\n", m_sid, free_cta_hw_id, gpu_sim_cycle, gpu_tot_sim_cycle ); + printf("GPGPU-Sim uArch: core:%3d, cta:%2u initialized @(%lld,%lld)\n", m_sid, free_cta_hw_id, gpu_sim_cycle, gpu_tot_sim_cycle ); } /////////////////////////////////////////////////////////////////////////////////////////// diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 2065f2d..903eb3c 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -319,7 +319,6 @@ private: class shader_core_stats *m_shader_stats; class memory_stats_t *m_memory_stats; unsigned long long gpu_tot_issued_cta; - unsigned long long gpu_tot_completed_thread; unsigned long long last_gpu_sim_insn; public: diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc index 5b4d3ac..e1cbe2b 100644 --- a/src/gpgpu-sim/mem_latency_stat.cc +++ b/src/gpgpu-sim/mem_latency_stat.cc @@ -258,7 +258,6 @@ void memory_stats_t::memlatstat_lat_pw( unsigned n_shader, unsigned n_thread_per for (i=0;i < ((n_shader * n_thread_per_shader / warp_size)+1); i++) { assert(igpgpu_memlatency_stat) { - assert(mf_tot_lat_pw_perwarp[i]); mf_total_lat_perwarp[i] += mf_tot_lat_pw_perwarp[i]; num_mfs_perwarp[i] += mf_num_lat_pw_perwarp[i]; mf_tot_lat_pw_perwarp[i] = 0; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 1b9ab0d..20910be 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -366,29 +366,18 @@ void pdom_warp_ctx_t::print (FILE *fout) const void shader_core_stats::print( FILE* fout ) const { - fprintf(fout,"gpu_sim_no_ld_const_insn = %lld\n", gpu_sim_insn_no_ld_const); - fprintf(fout,"gpu_completed_thread = %lld\n", gpu_completed_thread); - fprintf(fout,"gpu_stall_shd_mem = %d\n", gpu_stall_shd_mem ); - fprintf(fout,"gpu_stall_sh2icnt = %d\n", gpu_stall_sh2icnt ); - fprintf(fout,"L1 read misses = %d\n", L1_read_miss); - fprintf(fout,"L1 write misses = %d\n", L1_write_miss); - fprintf(fout,"L1 write hit on misses = %d\n", L1_write_hit_on_miss); - fprintf(fout,"L1 writebacks = %d\n", L1_writeback); - fprintf(fout,"L1 texture misses = %d\n", L1_texture_miss); - fprintf(fout,"L1 const misses = %d\n", L1_const_miss); + unsigned icount_uarch=0; + for(unsigned i=0; i < m_config->num_shader(); i++) { + icount_uarch += m_num_sim_insn[i]; + } + fprintf(fout,"gpgpu_n_tot_icount = %u\n", icount_uarch); + fprintf(fout,"gpgpu_n_stall_shd_mem = %d\n", gpgpu_n_stall_shd_mem ); fprintf(fout,"gpgpu_n_mem_read_local = %d\n", gpgpu_n_mem_read_local); fprintf(fout,"gpgpu_n_mem_write_local = %d\n", gpgpu_n_mem_write_local); fprintf(fout,"gpgpu_n_mem_read_global = %d\n", gpgpu_n_mem_read_global); fprintf(fout,"gpgpu_n_mem_write_global = %d\n", gpgpu_n_mem_write_global); fprintf(fout,"gpgpu_n_mem_texture = %d\n", gpgpu_n_mem_texture); fprintf(fout,"gpgpu_n_mem_const = %d\n", gpgpu_n_mem_const); - if( m_config->model == POST_DOMINATOR) { - fprintf(fout,"num_warps_issuable:"); - for (unsigned i=0;i<(m_config->max_warps_per_shader+1);i++) - fprintf(fout,"%d ", num_warps_issuable[i]); - fprintf(fout,"\n"); - } - fprintf(fout,"gpgpu_commit_pc_beyond_two = %d\n",gpgpu_commit_pc_beyond_two); /* unsigned a,m; for (unsigned i=0, a=0, m=0;in_simt_clusters;i++) - for (unsigned j=0;jn_simt_cores_per_cluster;j++) - gzprintf(visualizer_file, "%u ",m_cluster[i]->get_core(j)->get_core_stats()->m_icount); + for (unsigned i=0;inum_shader();i++) + gzprintf(visualizer_file, "%u ", m_num_sim_insn[i] ); gzprintf(visualizer_file, "\n"); // warp divergence per shader core gzprintf(visualizer_file, "shaderwarpdiv: "); - for (unsigned i=0;iget_n_diverge()); + for (unsigned i=0;inum_shader();i++) + gzprintf(visualizer_file, "%u ", m_n_diverge[i] ); gzprintf(visualizer_file, "\n"); -*/ /* gzprintf(visualizer_file, "CacheMissRate_GlobalLocalL1_All: "); @@ -650,7 +632,7 @@ void shader_core_ctx::issue_warp( warp_inst_t *&pipe_reg, const warp_inst_t *nex if( next_inst->op == BARRIER_OP ) m_barriers.warp_reaches_barrier(m_warp[warp_id].get_cta_id(),warp_id); else if( next_inst->op == MEMORY_BARRIER_OP ) - set_at_memory_barrier(warp_id); + m_warp[warp_id].set_membar(); m_pdom_warp[warp_id]->pdom_update_warp_mask(); m_scoreboard->reserveRegisters(pipe_reg); m_warp[warp_id].set_next_pc(next_inst->pc + next_inst->isize); @@ -721,18 +703,13 @@ void shader_core_ctx::decode() } } -// fprintf(fout, "Stall:%d\t", m_shader_stats->shader_cycle_distro[0]); -// fprintf(fout, "W0_Idle:%d\t", m_shader_stats->shader_cycle_distro[1]); -// fprintf(fout, "W0_Mem:%d", m_shader_stats->shader_cycle_distro[2]); - - // statistics: + // issue stall statistics: if( !valid_inst ) m_stats->shader_cycle_distro[0]++; // idle or control hazard else if( !ready_inst ) m_stats->shader_cycle_distro[1]++; // waiting for RAW hazards (possibly due to memory) else if( !issued_inst ) m_stats->shader_cycle_distro[2]++; // pipeline stalled - } address_type coalesced_segment(address_type addr, unsigned segment_size_lg2bytes) @@ -813,6 +790,7 @@ void shader_core_ctx::writeback() unsigned warp_id = pipe_reg->warp_id(); m_scoreboard->releaseRegisters( pipe_reg ); m_warp[warp_id].dec_inst_in_pipeline(); + m_stats->m_num_sim_insn[m_sid]++; m_gpu->gpu_sim_insn_last_update_sid = m_sid; m_gpu->gpu_sim_insn_last_update = gpu_sim_cycle; m_gpu->gpu_sim_insn += pipe_reg->active_count(); @@ -1026,9 +1004,12 @@ void ldst_unit::writeback() if( !still_pending ) { m_pending_writes[m_next_wb.warp_id()].erase(m_next_wb.out[r]); m_scoreboard->releaseRegister( m_next_wb.warp_id(), m_next_wb.out[r] ); + m_stats->m_num_sim_insn[m_sid]++; } - } else // shared + } else { // shared m_scoreboard->releaseRegister( m_next_wb.warp_id(), m_next_wb.out[r] ); + m_stats->m_num_sim_insn[m_sid]++; + } } } m_next_wb.clear(); @@ -1123,7 +1104,7 @@ void ldst_unit::cycle() m_mem_rc = rc_fail; if (!done) { // log stall types and return assert(rc_fail != NO_RC_FAIL); - m_stats->gpu_stall_shd_mem++; + m_stats->gpgpu_n_stall_shd_mem++; m_stats->gpu_stall_shd_mem_breakdown[type][rc_fail]++; return; } @@ -1154,8 +1135,10 @@ void ldst_unit::cycle() } } } - if( !pending_requests ) + if( !pending_requests ) { m_scoreboard->releaseRegisters(m_dispatch_reg); + m_stats->m_num_sim_insn[m_sid]++; + } m_core->dec_inst_in_pipeline(warp_id); m_dispatch_reg->clear(); } @@ -1163,6 +1146,7 @@ void ldst_unit::cycle() // stores exit pipeline here m_core->dec_inst_in_pipeline(warp_id); m_dispatch_reg->clear(); + m_stats->m_num_sim_insn[m_sid]++; } } } @@ -1177,7 +1161,7 @@ void shader_core_ctx::register_cta_thread_exit(int tid ) m_cta_status[cta_num]--; if (!m_cta_status[cta_num]) { m_n_active_cta--; - deallocate_barrier(cta_num); + m_barriers.deallocate_barrier(cta_num); shader_CTA_count_unlog(m_sid, 1); printf("GPGPU-Sim uArch: Shader %d finished CTA #%d (%lld,%lld)\n", m_sid, cta_num, gpu_sim_cycle, gpu_tot_sim_cycle ); } @@ -1661,11 +1645,6 @@ bool shader_core_ctx::warp_waiting_at_barrier( unsigned warp_id ) const return m_barriers.warp_waiting_at_barrier(warp_id); } -void shader_core_ctx::set_at_memory_barrier( unsigned warp_id ) -{ - m_warp[warp_id].set_membar(); -} - bool shader_core_ctx::warp_waiting_at_mem_barrier( unsigned warp_id ) { if( !m_warp[warp_id].get_membar() ) @@ -1682,16 +1661,6 @@ gpgpu_sim *shader_core_ctx::get_gpu() return m_gpu; } -void shader_core_ctx::allocate_barrier( unsigned cta_id, warp_set_t warps ) -{ - m_barriers.allocate_barrier(cta_id,warps); -} - -void shader_core_ctx::deallocate_barrier( unsigned cta_id ) -{ - m_barriers.deallocate_barrier(cta_id); -} - void shader_core_ctx::decrement_atomic_count( unsigned wid, unsigned n ) { assert( m_warp[wid].get_n_atomic() >= n ); @@ -1710,7 +1679,7 @@ void shader_core_ctx::accept_fetch_response( mem_fetch *mf ) m_L1I->fill(mf,gpu_sim_cycle+gpu_tot_sim_cycle); } -bool shader_core_ctx::ldst_unit_response_buffer_full() +bool shader_core_ctx::ldst_unit_response_buffer_full() const { return m_ldst_unit->response_buffer_full(); } @@ -1863,6 +1832,7 @@ void opndcoll_rfu_t::init( unsigned num_banks, shader_core_ctx *shader ) m_dispatch_units[m_output[n]].add_cu(&m_cu[c]); } } + m_initialized=true; } int register_bank(int regnum, int wid, unsigned num_banks, unsigned bank_warp_shift) diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index ce04e01..dd3d89e 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -314,6 +314,7 @@ public: m_cu = NULL; m_shader=NULL; m_num_ports=0; + m_initialized=false; } void add_port( unsigned num_collector_units, warp_inst_t **input_port, @@ -325,11 +326,11 @@ public: void step() { - dispatch_ready_cu(); - allocate_reads(); - for( unsigned p=0; p < m_num_ports; p++ ) - allocate_cu( p ); - process_banks(); + dispatch_ready_cu(); + allocate_reads(); + for( unsigned p=0; p < m_num_ports; p++ ) + allocate_cu( p ); + process_banks(); } void dump( FILE *fp ) const @@ -462,6 +463,7 @@ private: _inmatch=NULL; _outmatch=NULL; _request=NULL; + m_last_cu=0; } void init( unsigned num_cu, unsigned num_banks ) { @@ -645,13 +647,14 @@ private: }; // opndcoll_rfu_t data members + bool m_initialized; - unsigned m_num_collectors; - unsigned m_num_banks; - unsigned m_bank_warp_shift; - unsigned m_warp_size; - collector_unit_t *m_cu; - arbiter_t m_arbiter; + unsigned m_num_collectors; + unsigned m_num_banks; + unsigned m_bank_warp_shift; + unsigned m_warp_size; + collector_unit_t *m_cu; + arbiter_t m_arbiter; unsigned m_num_ports; std::vector m_input; @@ -972,45 +975,36 @@ struct shader_core_config : public core_config }; struct shader_core_stats_pod { - unsigned gpgpu_n_load_insn; - unsigned gpgpu_n_store_insn; - unsigned gpgpu_n_shmem_insn; - unsigned gpgpu_n_tex_insn; - unsigned gpgpu_n_const_insn; - unsigned gpgpu_n_param_insn; - unsigned gpgpu_n_shmem_bkconflict; - unsigned gpgpu_n_cache_bkconflict; - int gpgpu_n_intrawarp_mshr_merge; - unsigned gpgpu_n_cmem_portconflict; - unsigned gpu_stall_shd_mem_breakdown[N_MEM_STAGE_ACCESS_TYPE][N_MEM_STAGE_STALL_TYPE]; - unsigned gpu_reg_bank_conflict_stalls; - unsigned *shader_cycle_distro; - unsigned *last_shader_cycle_distro; - unsigned L1_write_miss; - unsigned L1_read_miss; - unsigned L1_texture_miss; - unsigned L1_const_miss; - unsigned L1_write_hit_on_miss; - unsigned L1_writeback; - unsigned long long gpu_sim_insn_no_ld_const; - unsigned long long gpu_completed_thread; - unsigned gpgpu_commit_pc_beyond_two; - unsigned gpu_stall_shd_mem; - unsigned gpu_stall_sh2icnt; - int *num_warps_issuable; - int *num_warps_issuable_pershader; - - //memory access classification - int gpgpu_n_mem_read_local; - int gpgpu_n_mem_write_local; - int gpgpu_n_mem_texture; - int gpgpu_n_mem_const; - int gpgpu_n_mem_read_global; - int gpgpu_n_mem_write_global; - int gpgpu_n_mem_read_inst; - - unsigned made_write_mfs; - unsigned made_read_mfs; + unsigned *m_num_sim_insn; // number of instructions committed by this shader core + unsigned *m_n_diverge; // number of divergence occurring in this shader + unsigned gpgpu_n_load_insn; + unsigned gpgpu_n_store_insn; + unsigned gpgpu_n_shmem_insn; + unsigned gpgpu_n_tex_insn; + unsigned gpgpu_n_const_insn; + unsigned gpgpu_n_param_insn; + unsigned gpgpu_n_shmem_bkconflict; + unsigned gpgpu_n_cache_bkconflict; + int gpgpu_n_intrawarp_mshr_merge; + unsigned gpgpu_n_cmem_portconflict; + unsigned gpu_stall_shd_mem_breakdown[N_MEM_STAGE_ACCESS_TYPE][N_MEM_STAGE_STALL_TYPE]; + unsigned gpu_reg_bank_conflict_stalls; + unsigned *shader_cycle_distro; + unsigned *last_shader_cycle_distro; + unsigned *num_warps_issuable; + unsigned gpgpu_n_stall_shd_mem; + + //memory access classification + int gpgpu_n_mem_read_local; + int gpgpu_n_mem_write_local; + int gpgpu_n_mem_texture; + int gpgpu_n_mem_const; + int gpgpu_n_mem_read_global; + int gpgpu_n_mem_write_global; + int gpgpu_n_mem_read_inst; + + unsigned made_write_mfs; + unsigned made_read_mfs; }; class shader_core_stats : private shader_core_stats_pod { @@ -1021,20 +1015,17 @@ public: shader_core_stats_pod *pod = this; memset(pod,0,sizeof(shader_core_stats_pod)); - num_warps_issuable = (int*) calloc(config->max_warps_per_shader+1, sizeof(int)); - num_warps_issuable_pershader = (int*) calloc(config->n_simt_clusters*config->n_simt_cores_per_cluster, sizeof(int)); - shader_cycle_distro = (unsigned int*) calloc(config->warp_size+3, sizeof(unsigned int)); - last_shader_cycle_distro = (unsigned int*) calloc(m_config->warp_size+3, sizeof(unsigned int)); + m_num_sim_insn = (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); + m_n_diverge = (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); + shader_cycle_distro = (unsigned*) calloc(config->warp_size+3, sizeof(unsigned)); + last_shader_cycle_distro = (unsigned*) calloc(m_config->warp_size+3, sizeof(unsigned)); } void new_grid() { - gpu_sim_insn_no_ld_const = 0; - gpu_completed_thread = 0; } void visualizer_print( gzFile visualizer_file ); - unsigned long long get_gpu_completed_thread() const { return gpu_completed_thread; } void print( FILE *fout ) const; private: @@ -1045,126 +1036,125 @@ private: friend class simt_core_cluster; }; -class shader_core_ctx : public core_t -{ +class shader_core_ctx : public core_t { public: - shader_core_ctx( class gpgpu_sim *gpu, - class simt_core_cluster *cluster, - unsigned shader_id, - unsigned tpc_id, - const struct shader_core_config *config, - const struct memory_config *mem_config, - shader_core_stats *stats ); - - void issue_block2core( class kernel_info_t &kernel ); - void get_pdom_stack_top_info( unsigned tid, unsigned *pc, unsigned *rpc ) const; - bool ptx_thread_done( unsigned hw_thread_id ) const; - class ptx_thread_info *get_thread_state( unsigned hw_thread_id ); - void mem_instruction_stats(const warp_inst_t &inst); - - virtual void warp_exit( unsigned warp_id ); - virtual bool warp_waiting_at_barrier( unsigned warp_id ) const; - virtual class gpgpu_sim *get_gpu(); - void set_at_memory_barrier( unsigned warp_id ); - bool warp_waiting_at_mem_barrier( unsigned warp_id ); - void allocate_barrier( unsigned cta_id, warp_set_t warps ); - void deallocate_barrier( unsigned cta_id ); - void decrement_atomic_count( unsigned wid, unsigned n ); - - void cycle(); - - void reinit(unsigned start_thread, unsigned end_thread, bool reset_not_completed ); - void init_warps(unsigned cta_id, unsigned start_thread, unsigned end_thread); - - void cache_flush(); - void display_pdom_state(FILE *fout, int mask ) const; - void display_pipeline( FILE *fout, int print_mem, int mask3bit ) const; - void register_cta_thread_exit(int cta_num ); - bool fetch_unit_response_buffer_full() const; - void accept_fetch_response( mem_fetch *mf ); - bool ldst_unit_response_buffer_full(); - void accept_ldst_unit_response( class mem_fetch * mf ); - void store_ack( class mem_fetch *mf ); - - class ptx_thread_info* get_functional_thread( unsigned tid ) { return m_thread[tid].m_functional_model_thread_state; } - std::list get_regs_written( const inst_t &fvt ) const; - const shader_core_config *get_config() const { return m_config; } - unsigned get_num_sim_insn() const { return m_num_sim_insn; } - int get_not_completed() const { return m_not_completed; } - unsigned get_n_diverge() const { return m_n_diverge; } - unsigned get_thread_n_insn( unsigned tid ) const { return m_thread[tid].n_insn; } - unsigned get_thread_n_insn_ac( unsigned tid ) const { return m_thread[tid].n_insn_ac; } - unsigned get_thread_n_l1_mis_ac( unsigned tid ) const { return m_thread[tid].n_l1_mis_ac; } - unsigned get_thread_n_l1_mrghit_ac( unsigned tid ) const { return m_thread[tid].n_l1_mrghit_ac; } - unsigned get_thread_n_l1_access_ac( unsigned tid ) const { return m_thread[tid].n_l1_access_ac; } - unsigned get_n_active_cta() const { return m_n_active_cta; } - void inc_store_req( unsigned warp_id) { m_warp[warp_id].inc_store_req(); } - void dec_inst_in_pipeline( unsigned warp_id ) { m_warp[warp_id].dec_inst_in_pipeline(); } - -private: - void dump_istream_state( FILE *fout ) const; + // creator: + shader_core_ctx( class gpgpu_sim *gpu, + class simt_core_cluster *cluster, + unsigned shader_id, + unsigned tpc_id, + const struct shader_core_config *config, + const struct memory_config *mem_config, + shader_core_stats *stats ); + +// used by simt_core_cluster: + // modifiers + void cycle(); + void reinit(unsigned start_thread, unsigned end_thread, bool reset_not_completed ); + void issue_block2core( class kernel_info_t &kernel ); + void cache_flush(); + void accept_fetch_response( mem_fetch *mf ); + void accept_ldst_unit_response( class mem_fetch * mf ); + + // accessors + bool fetch_unit_response_buffer_full() const; + bool ldst_unit_response_buffer_full() const; + unsigned get_not_completed() const { return m_not_completed; } + unsigned get_n_active_cta() const { return m_n_active_cta; } - address_type next_pc( int tid ) const; +// used by functional simulation: + // modifiers + virtual void warp_exit( unsigned warp_id ); + class ptx_thread_info *get_thread_state( unsigned hw_thread_id ); + virtual class gpgpu_sim *get_gpu(); + + // accessors + virtual bool warp_waiting_at_barrier( unsigned warp_id ) const; + void get_pdom_stack_top_info( unsigned tid, unsigned *pc, unsigned *rpc ) const; + bool ptx_thread_done( unsigned hw_thread_id ) const; - void fetch(); +// used by pipeline timing model components: + // modifiers + void mem_instruction_stats(const warp_inst_t &inst); + void decrement_atomic_count( unsigned wid, unsigned n ); + void inc_store_req( unsigned warp_id) { m_warp[warp_id].inc_store_req(); } + void dec_inst_in_pipeline( unsigned warp_id ) { m_warp[warp_id].dec_inst_in_pipeline(); } // also used in writeback() + void store_ack( class mem_fetch *mf ); + bool warp_waiting_at_mem_barrier( unsigned warp_id ); + + // accessors + std::list get_regs_written( const inst_t &fvt ) const; + const shader_core_config *get_config() const { return m_config; } - void decode(); - void issue_warp( warp_inst_t *&warp, const warp_inst_t *pI, unsigned active_mask, unsigned warp_id ); - void func_exec_inst( warp_inst_t &inst ); - address_type translate_local_memaddr(address_type localaddr, unsigned tid, unsigned num_shader ); +// debug: + void display_pdom_state(FILE *fout, int mask ) const; + void display_pipeline( FILE *fout, int print_mem, int mask3bit ) const; - void execute(); +private: + void init_warps(unsigned cta_id, unsigned start_thread, unsigned end_thread); - void writeback(); + address_type next_pc( int tid ) const; + + void fetch(); + void register_cta_thread_exit(int cta_num ); + + void decode(); + void issue_warp( warp_inst_t *&warp, const warp_inst_t *pI, unsigned active_mask, unsigned warp_id ); + void func_exec_inst( warp_inst_t &inst ); + address_type translate_local_memaddr(address_type localaddr, unsigned tid, unsigned num_shader ); + + void execute(); + + void writeback(); + + // used in display_pipeline(): + void dump_istream_state( FILE *fout ) const; + void print_stage(unsigned int stage, FILE *fout) const; - void print_stage(unsigned int stage, FILE *fout) const; + // general information + unsigned m_sid; // shader id + unsigned m_tpc; // texture processor cluster id (aka, node id when using interconnect concentration) + const shader_core_config *m_config; + const memory_config *m_memory_config; + class simt_core_cluster *m_cluster; + class gpgpu_sim *m_gpu; + + // statistics + shader_core_stats *m_stats; - // general information - unsigned m_sid; // shader id - unsigned m_tpc; // texture processor cluster id (aka, node id when using interconnect concentration) - const shader_core_config *m_config; - const memory_config *m_memory_config; - class simt_core_cluster *m_cluster; - class gpgpu_sim *m_gpu; - - // statistics - shader_core_stats *m_stats; - unsigned int m_num_sim_insn; // number of instructions committed by this shader core - unsigned int m_n_diverge; // number of divergence occurred in this shader - - // CTA scheduling / hardware thread allocation - int m_n_active_cta; // number of Cooperative Thread Arrays (blocks) currently running on this shader. - int m_cta_status[MAX_CTA_PER_SHADER]; // CTAs status - int m_not_completed; // number of threads to be completed (==0 when all thread on this core completed) - - // thread contexts - thread_ctx_t *m_thread; // functional state, per thread fetch state - - // interconnect interface - shader_memory_interface *m_icnt; - - // fetch - read_only_cache *m_L1I; // instruction cache - int m_last_warp_fetched; - - // decode/dispatch - int m_last_warp_issued; - std::vector m_warp; // per warp information array - barrier_set_t m_barriers; - ifetch_buffer_t m_inst_fetch_buffer; - pdom_warp_ctx_t **m_pdom_warp; // pdom reconvergence context for each warp - warp_inst_t** m_pipeline_reg; - Scoreboard *m_scoreboard; - opndcoll_rfu_t m_operand_collector; - - // execute - unsigned m_num_function_units; - enum pipeline_stage_name_t *m_dispatch_port; - enum pipeline_stage_name_t *m_issue_port; - simd_function_unit **m_fu; // stallable pipelines should be last in this array - ldst_unit *m_ldst_unit; - static const unsigned MAX_ALU_LATENCY = 64; - std::bitset m_result_bus; + // CTA scheduling / hardware thread allocation + unsigned m_n_active_cta; // number of Cooperative Thread Arrays (blocks) currently running on this shader. + unsigned m_cta_status[MAX_CTA_PER_SHADER]; // CTAs status + unsigned m_not_completed; // number of threads to be completed (==0 when all thread on this core completed) + + // thread contexts + thread_ctx_t *m_thread; // functional state, per thread fetch state + + // interconnect interface + shader_memory_interface *m_icnt; + + // fetch + read_only_cache *m_L1I; // instruction cache + int m_last_warp_fetched; + + // decode/dispatch + int m_last_warp_issued; + std::vector m_warp; // per warp information array + barrier_set_t m_barriers; + ifetch_buffer_t m_inst_fetch_buffer; + pdom_warp_ctx_t **m_pdom_warp; // pdom reconvergence context for each warp + warp_inst_t** m_pipeline_reg; + Scoreboard *m_scoreboard; + opndcoll_rfu_t m_operand_collector; + + // execute + unsigned m_num_function_units; + enum pipeline_stage_name_t *m_dispatch_port; + enum pipeline_stage_name_t *m_issue_port; + simd_function_unit **m_fu; // stallable pipelines should be last in this array + ldst_unit *m_ldst_unit; + static const unsigned MAX_ALU_LATENCY = 64; + std::bitset m_result_bus; }; class simt_core_cluster { -- cgit v1.3