From f76b1aaeea5077e83f95ef39564e73bcbec25b37 Mon Sep 17 00:00:00 2001 From: Tim Rogers Date: Thu, 27 Oct 2011 09:01:15 -0800 Subject: Fixing the varying instruction count when the cache configuration changes. The problem was 2-fold: 1) If all the lanes hit, we were not incrementing the instruction count since the instruction did not progress to the WB stage, the scoreboard relasing is done in the ldst_unit::cycle function for cache hits. Added code there to increment the instrcution count. 2) Loads were some lanes hit in cache and some lanes do not were not being comepletely counted. Only the lanes sent off to the memory system were being counted because we were setting the warp's active lanes to the access's acrtive lanes.... I am not sure why this code was there... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10737] --- src/gpgpu-sim/shader.cc | 5 ++++- src/gpgpu-sim/shader.h | 3 ++- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'src/gpgpu-sim') diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 19c2291..50ad5ea 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1089,14 +1089,15 @@ void ldst_unit::writeback() m_pending_writes[m_next_wb.warp_id()].erase(m_next_wb.out[r]); m_scoreboard->releaseRegister( m_next_wb.warp_id(), m_next_wb.out[r] ); m_stats->m_num_sim_insn[m_sid]++; + m_core->get_gpu()->gpu_sim_insn += m_next_wb.active_count(); } } else { // shared m_scoreboard->releaseRegister( m_next_wb.warp_id(), m_next_wb.out[r] ); m_stats->m_num_sim_insn[m_sid]++; + m_core->get_gpu()->gpu_sim_insn += m_next_wb.active_count(); } } } - m_core->get_gpu()->gpu_sim_insn += m_next_wb.active_count(); m_next_wb.clear(); m_last_inst_gpu_sim_cycle = gpu_sim_cycle; m_last_inst_gpu_tot_sim_cycle = gpu_tot_sim_cycle; @@ -1234,6 +1235,7 @@ void ldst_unit::cycle() } } if( !pending_requests ) { + m_core->get_gpu()->gpu_sim_insn += m_dispatch_reg->active_count(); m_scoreboard->releaseRegisters(m_dispatch_reg); m_stats->m_num_sim_insn[m_sid]++; } @@ -1243,6 +1245,7 @@ void ldst_unit::cycle() } else { // stores exit pipeline here m_core->dec_inst_in_pipeline(warp_id); + m_core->get_gpu()->gpu_sim_insn += m_dispatch_reg->active_count(); m_dispatch_reg->clear(); m_stats->m_num_sim_insn[m_sid]++; } diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index dcb24be..e7d2f1b 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1110,7 +1110,8 @@ public: mem_fetch *alloc( const warp_inst_t &inst, const mem_access_t &access ) const { warp_inst_t inst_copy = inst; - inst_copy.set_active(access.get_warp_mask()); + // tgrogers Oct 27, 2011 - I am commenting out this line of code, because it is screwing up our instruction counts on memory instructions. I am not sure what the point of this was, because no one seems to read the active mask on the memory fetches's warp instruction. + //inst_copy.set_active(access.get_warp_mask()); mem_fetch *mf = new mem_fetch(access, &inst_copy, access.is_write()?WRITE_PACKET_SIZE:READ_PACKET_SIZE, -- cgit v1.3