From b0cf792926caf74b393a14e36de676c7afd68164 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Tue, 12 Oct 2010 00:46:24 -0800 Subject: 1. adding simt_core_cluster, which models a TPC or (for fermi) GPC... this gives us a place to stick caches shared among shader cores but on the shader side of the interconnect... maybe move the clock boundary code here? after integrating booksim 2 code? 2. added a pending write table to ldst_unit rather than scoreboard ... rationale is that ld/st unit needs to process register writes once it is done it can notify scoreboard once. 3. re-enabled shared memory delay (use pipeline within ldst_unit) 4. re-enabling operand collector writeback for all instruction types 5. disable MSHRs in this change list passing CUDA 3.1 regression next? texture cache, then redo mshrs? [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845] --- src/gpgpusim_entrypoint.cc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/gpgpusim_entrypoint.cc') diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index 6f13cd2..f6dea90 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -95,9 +95,7 @@ void *gpgpu_sim_thread(void*) { do { sem_wait(&g_sim_signal_start); - unsigned grid; - class function_info *entry; - g_the_gpu.next_grid(grid,entry); + g_the_gpu.next_grid(); g_the_gpu.run_gpu_sim(); print_simulation_time(); sem_post(&g_sim_signal_finish); -- cgit v1.3