From 8c087fa6baa2268a2675c3fec772f2bd696f080e Mon Sep 17 00:00:00 2001 From: Ahmed El-Shafiey Date: Fri, 25 Jan 2013 00:07:31 -0800 Subject: fixing bug 36 + put a mistakenly missing texture misses power scaling [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15105] --- src/gpuwattch/gpgpu_sim_wrapper.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gpuwattch/gpgpu_sim_wrapper.cc') diff --git a/src/gpuwattch/gpgpu_sim_wrapper.cc b/src/gpuwattch/gpgpu_sim_wrapper.cc index ffd4650..22d0659 100644 --- a/src/gpuwattch/gpgpu_sim_wrapper.cc +++ b/src/gpuwattch/gpgpu_sim_wrapper.cc @@ -275,7 +275,7 @@ void gpgpu_sim_wrapper::set_ccache_power(double hits, double misses) void gpgpu_sim_wrapper::set_tcache_power(double hits, double misses) { p->sys.core[0].tcache.read_accesses = hits * p->sys.scaling_coefficients[TC_H]+misses * p->sys.scaling_coefficients[TC_M]; - p->sys.core[0].tcache.read_misses = misses; + p->sys.core[0].tcache.read_misses = misses* p->sys.scaling_coefficients[TC_M]; perf_count[TC_H]=hits; perf_count[TC_M]=misses; // TODO: coalescing logic is counted as part of the caches power (this is not valid for no-caches architectures) -- cgit v1.3