From 69f2911e04ffb1b19eef1fafb8c040af271f656e Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Thu, 15 Jul 2010 18:09:46 -0800 Subject: creating branch for adding support for CUDA 3.x and Fermi [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6829] --- src/intersim/examples/fly26_age | 41 ++++++++++++++++++++++++++++++++++++++++ src/intersim/examples/mesh | 40 +++++++++++++++++++++++++++++++++++++++ src/intersim/examples/mesh2 | 41 ++++++++++++++++++++++++++++++++++++++++ src/intersim/examples/mesh4 | 41 ++++++++++++++++++++++++++++++++++++++++ src/intersim/examples/mesh88_lat | 40 +++++++++++++++++++++++++++++++++++++++ src/intersim/examples/single | 20 ++++++++++++++++++++ src/intersim/examples/torus88 | 14 ++++++++++++++ 7 files changed, 237 insertions(+) create mode 100644 src/intersim/examples/fly26_age create mode 100644 src/intersim/examples/mesh create mode 100644 src/intersim/examples/mesh2 create mode 100644 src/intersim/examples/mesh4 create mode 100644 src/intersim/examples/mesh88_lat create mode 100644 src/intersim/examples/single create mode 100644 src/intersim/examples/torus88 (limited to 'src/intersim/examples') diff --git a/src/intersim/examples/fly26_age b/src/intersim/examples/fly26_age new file mode 100644 index 0000000..1abff5d --- /dev/null +++ b/src/intersim/examples/fly26_age @@ -0,0 +1,41 @@ +// Topology + +topology = fly; +k = 2; +n = 6; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 8; +vc_buf_size = 8; + +wait_for_tail_credit = 1; + +// Router architecture + +vc_allocator = select; +sw_allocator = select; +alloc_iters = 1; + +credit_delay = 2; +routing_delay = 1; +vc_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic + +traffic = uniform; +const_flits_per_packet = 20; +priority = age; + +// Simulation + +sim_type = latency; +injection_rate = 0.1; \ No newline at end of file diff --git a/src/intersim/examples/mesh b/src/intersim/examples/mesh new file mode 100644 index 0000000..b374981 --- /dev/null +++ b/src/intersim/examples/mesh @@ -0,0 +1,40 @@ +// Topology + +topology = mesh; +k = 2; +n = 2; + +// Routing + +routing_function = dim_order; + +// Flow control + +num_vcs = 8; +vc_buf_size = 8; + +wait_for_tail_credit = 1; + +// Router architecture + +vc_allocator = islip; +sw_allocator = islip; +alloc_iters = 1; + +credit_delay = 1; +routing_delay = 1; +vc_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic + +traffic = transpose; +const_flits_per_packet = 20; + +// Simulation + +sim_type = latency; +injection_rate = 0.1; diff --git a/src/intersim/examples/mesh2 b/src/intersim/examples/mesh2 new file mode 100644 index 0000000..8eb0521 --- /dev/null +++ b/src/intersim/examples/mesh2 @@ -0,0 +1,41 @@ +// Topology + +topology = mesh; +k = 2; +n = 2; + +// Routing + +routing_function = dim_order; + +// Flow control + +num_vcs = 8; +vc_buf_size = 8; + +wait_for_tail_credit = 1; + +// Router architecture + +vc_allocator = islip; +sw_allocator = islip; +alloc_iters = 1; + +credit_delay = 1; +routing_delay = 1; +vc_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic + +traffic = gpgpusim; +const_flits_per_packet = 3; + +injection_process = gpgpu_injector; +// Simulation + +sim_type = latency; +injection_rate = 0.1; diff --git a/src/intersim/examples/mesh4 b/src/intersim/examples/mesh4 new file mode 100644 index 0000000..8492df6 --- /dev/null +++ b/src/intersim/examples/mesh4 @@ -0,0 +1,41 @@ +// Topology + +topology = mesh; +k = 2; +n = 1; + +// Routing + +routing_function = dim_order; + +// Flow control + +num_vcs = 1; +vc_buf_size = 1; + +wait_for_tail_credit = 1; + +// Router architecture + +vc_allocator = islip; +sw_allocator = islip; +alloc_iters = 1; + +credit_delay = 1; +routing_delay = 1; +vc_alloc_delay = 1; + +input_speedup = 1; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic + +traffic = gpgpusim; +const_flits_per_packet = 3; + +injection_process = gpgpu_injector; +// Simulation + +sim_type = latency; +injection_rate = 0.1; diff --git a/src/intersim/examples/mesh88_lat b/src/intersim/examples/mesh88_lat new file mode 100644 index 0000000..fca1fb4 --- /dev/null +++ b/src/intersim/examples/mesh88_lat @@ -0,0 +1,40 @@ +// Topology + +topology = mesh; +k = 8; +n = 2; + +// Routing + +routing_function = dim_order; + +// Flow control + +num_vcs = 8; +vc_buf_size = 8; + +wait_for_tail_credit = 1; + +// Router architecture + +vc_allocator = islip; +sw_allocator = islip; +alloc_iters = 1; + +credit_delay = 2; +routing_delay = 1; +vc_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic + +traffic = transpose; +const_flits_per_packet = 20; + +// Simulation + +sim_type = latency; +injection_rate = 0.1; \ No newline at end of file diff --git a/src/intersim/examples/single b/src/intersim/examples/single new file mode 100644 index 0000000..addb549 --- /dev/null +++ b/src/intersim/examples/single @@ -0,0 +1,20 @@ +// Topology + +topology = single; +in_ports = 8; +out_ports = 8; + +// Routing + +routing_function = single; + +// Flow control + +vc_allocator = islip; +sw_allocator = islip; +alloc_iters = 2; + +num_vcs = 8; +vc_buf_size = 1000; + +wait_for_tail_credit = 0; \ No newline at end of file diff --git a/src/intersim/examples/torus88 b/src/intersim/examples/torus88 new file mode 100644 index 0000000..723e3ac --- /dev/null +++ b/src/intersim/examples/torus88 @@ -0,0 +1,14 @@ +// Topology +topology = torus; +k = 8; +n = 2; + +// Routing +routing_function = dim_order; + +// Flow control +num_vcs = 2; + +// Traffic +traffic = uniform; +injection_rate = 0.15; -- cgit v1.3