From e0f1b4359832ba2952ddcff3a400cd7e1e3d02b5 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Tue, 5 Oct 2010 13:34:47 -0800 Subject: broken change list: builds, but does not run, yet refactoring: create warp_inst_t that provides notion of a group of scalar instructions traveling down the pipeline. delete DWF delete MIMD delete warp_tracker delete old writeback stage, replace it with a stub that just writes back everything delete old pipeline model current status: MSHR's need to change to deal with the new structure [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7814] --- src/intersim/interconnect_interface.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/intersim/interconnect_interface.cpp') diff --git a/src/intersim/interconnect_interface.cpp b/src/intersim/interconnect_interface.cpp index 56b2d18..0ed7150 100644 --- a/src/intersim/interconnect_interface.cpp +++ b/src/intersim/interconnect_interface.cpp @@ -556,7 +556,7 @@ void time_vector_update_icnt_injected(void* data, int input) { mem_fetch* mf = (mem_fetch*) data; if( mf->get_mshr() && !mf->get_mshr()->isinst() ) { - unsigned uid=mf->get_is_write()? mf->get_request_uid() : mf->get_mshr()->get_insts_uid(); + unsigned uid=mf->get_request_uid(); long int cycle = gpu_sim_cycle + gpu_tot_sim_cycle; int req_type = mf->get_is_write()? WT_REQ : RD_REQ; if (is_mem(input)) { -- cgit v1.3