From b0cf792926caf74b393a14e36de676c7afd68164 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Tue, 12 Oct 2010 00:46:24 -0800 Subject: 1. adding simt_core_cluster, which models a TPC or (for fermi) GPC... this gives us a place to stick caches shared among shader cores but on the shader side of the interconnect... maybe move the clock boundary code here? after integrating booksim 2 code? 2. added a pending write table to ldst_unit rather than scoreboard ... rationale is that ld/st unit needs to process register writes once it is done it can notify scoreboard once. 3. re-enabled shared memory delay (use pipeline within ldst_unit) 4. re-enabling operand collector writeback for all instruction types 5. disable MSHRs in this change list passing CUDA 3.1 regression next? texture cache, then redo mshrs? [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845] --- src/intersim/interconnect_interface.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/intersim/interconnect_interface.h') diff --git a/src/intersim/interconnect_interface.h b/src/intersim/interconnect_interface.h index 3e3826d..9003fc6 100644 --- a/src/intersim/interconnect_interface.h +++ b/src/intersim/interconnect_interface.h @@ -13,7 +13,7 @@ struct glue_buf { }; //node side functions -int interconnect_has_buffer(unsigned int input, unsigned int size); +bool interconnect_has_buffer(unsigned int input, unsigned int size); void interconnect_push ( unsigned int input, unsigned int output, void* data, unsigned int size); void* interconnect_pop(unsigned int output); -- cgit v1.3