From bdc0e550448f04c7c8f030b7421209bae37e651d Mon Sep 17 00:00:00 2001 From: Dongdong Li Date: Fri, 22 Nov 2013 11:32:14 -0800 Subject: Add .svn file so other people can keep update with changes from Stanford Code Review: Issue 103001 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17411] --- ...7cc0dc517c023ddeaf70f92c90e0ecfe343030.svn-base | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 src/intersim2/.svn/pristine/f4/f47cc0dc517c023ddeaf70f92c90e0ecfe343030.svn-base (limited to 'src/intersim2/.svn/pristine/f4/f47cc0dc517c023ddeaf70f92c90e0ecfe343030.svn-base') diff --git a/src/intersim2/.svn/pristine/f4/f47cc0dc517c023ddeaf70f92c90e0ecfe343030.svn-base b/src/intersim2/.svn/pristine/f4/f47cc0dc517c023ddeaf70f92c90e0ecfe343030.svn-base new file mode 100644 index 0000000..c953713 --- /dev/null +++ b/src/intersim2/.svn/pristine/f4/f47cc0dc517c023ddeaf70f92c90e0ecfe343030.svn-base @@ -0,0 +1,26 @@ +// 2007 ITRS predictions for a 32nm high-performance library +H_INVD2 = 8;//int +W_INVD2 = 3;//int +H_DFQD1 = 8;//int +W_DFQD1 = 16;//int +H_ND2D1 = 8;//int +W_ND2D1 = 3;//int +H_SRAM = 8;//int +W_SRAM = 6;//int +Vdd = 0.9;//float +R = 606.321;//float +IoffSRAM = 0.00000032;//float +// 70 C +IoffP = 0.00000102;//float +IoffN = 0.00000102;//float +Cg_pwr = 0.000000000000000534;//float +Cd_pwr = 0.000000000000000267;//float +Cgdl = 0.0000000000000001068;//float +Cg = 0.000000000000000534;//float +Cd = 0.000000000000000267;//float +LAMBDA = 0.016;//float +MetalPitch = 0.000080;//float +Rw = 0.720044;//float +Cw_gnd = 0.000000000000267339;//float +Cw_cpl = 0.000000000000267339;//float +wire_length = 2.0;//float \ No newline at end of file -- cgit v1.3