From b0cf792926caf74b393a14e36de676c7afd68164 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Tue, 12 Oct 2010 00:46:24 -0800 Subject: 1. adding simt_core_cluster, which models a TPC or (for fermi) GPC... this gives us a place to stick caches shared among shader cores but on the shader side of the interconnect... maybe move the clock boundary code here? after integrating booksim 2 code? 2. added a pending write table to ldst_unit rather than scoreboard ... rationale is that ld/st unit needs to process register writes once it is done it can notify scoreboard once. 3. re-enabled shared memory delay (use pipeline within ldst_unit) 4. re-enabling operand collector writeback for all instruction types 5. disable MSHRs in this change list passing CUDA 3.1 regression next? texture cache, then redo mshrs? [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845] --- src/intersim/interconnect_interface.cpp | 36 ++++++++++++++++++++++++--------- src/intersim/interconnect_interface.h | 2 +- 2 files changed, 27 insertions(+), 11 deletions(-) (limited to 'src/intersim') diff --git a/src/intersim/interconnect_interface.cpp b/src/intersim/interconnect_interface.cpp index 0ed7150..5d3d55c 100644 --- a/src/intersim/interconnect_interface.cpp +++ b/src/intersim/interconnect_interface.cpp @@ -67,6 +67,18 @@ public: } return data; } + void * top_packet(){ + assert (packet_n); + void * data = NULL; + void * temp_d = buf.front(); + while (data==NULL) { + if (tail_flag.front()) { + data = buf.front(); + } + assert(temp_d == buf.front()); //all flits must belong to the same packet + } + return data; + } void push_flit_data(void* data,bool is_tail) { buf.push(data); tail_flag.push(is_tail); @@ -130,17 +142,19 @@ void map_gen(int dim,int memcount, int memnodes[]) assert(k==dim*dim); } -void display_map(int dim,int count){ +void display_map(int dim,int count) +{ + printf("GPGPU-Sim uArch: "); int i=0; for (i=0;i_partial_packets[input][0].size() + n_flits) <= input_buffer_capacity; if ((net_c>1) && is_mem(input)) has_buffer = (traffic[1]->_partial_packets[input][0].size() + n_flits) <= input_buffer_capacity; } else { - has_buffer = 1; + has_buffer = true; } return has_buffer; } @@ -554,6 +568,7 @@ void time_vector_update(unsigned int uid, int slot , long int cycle, int type); void time_vector_update_icnt_injected(void* data, int input) { + /* mem_fetch* mf = (mem_fetch*) data; if( mf->get_mshr() && !mf->get_mshr()->isinst() ) { unsigned uid=mf->get_request_uid(); @@ -565,4 +580,5 @@ void time_vector_update_icnt_injected(void* data, int input) time_vector_update( uid, MR_ICNT_INJECTED, cycle,req_type ); } } + */ } diff --git a/src/intersim/interconnect_interface.h b/src/intersim/interconnect_interface.h index 3e3826d..9003fc6 100644 --- a/src/intersim/interconnect_interface.h +++ b/src/intersim/interconnect_interface.h @@ -13,7 +13,7 @@ struct glue_buf { }; //node side functions -int interconnect_has_buffer(unsigned int input, unsigned int size); +bool interconnect_has_buffer(unsigned int input, unsigned int size); void interconnect_push ( unsigned int input, unsigned int output, void* data, unsigned int size); void* interconnect_pop(unsigned int output); -- cgit v1.3