From b577cbcdf229a2c02d1bf8584c6e82be7a14cb33 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sat, 16 Oct 2010 17:30:52 -0800 Subject: 1. creating cache_config object to encapsulate cache configuration information (and parse it before creating the simulator objects). 2. creating core_config to hold only features of a shader_core that are high level enough either (a) the functional simulator needs to know about them, or (b) they affect memory *access* generation. 3. in config files only (so far) separate out notion of write-{through,back}, from notion of when a line is allocated... will use this to distinguish different types of caches. passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7870] --- src/intersim/interconnect_interface.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/intersim') diff --git a/src/intersim/interconnect_interface.cpp b/src/intersim/interconnect_interface.cpp index 5d3d55c..1b4ffea 100644 --- a/src/intersim/interconnect_interface.cpp +++ b/src/intersim/interconnect_interface.cpp @@ -465,9 +465,8 @@ void init_interconnect (char* config_file, if (icnt_config.GetInt("input_buf_size")) { input_buffer_capacity = icnt_config.GetInt("input_buf_size"); } else { - if (shader_config->gpgpu_cache_dl1_opt && !shader_config->gpgpu_no_dl1) { - int l1cache_linesize = 32; - sscanf(shader_config->gpgpu_cache_dl1_opt,"%*d:%d:%*d:%*c", &l1cache_linesize); + if (shader_config->m_L1D_config.get_num_lines() && !shader_config->gpgpu_no_dl1) { + int l1cache_linesize = shader_config->m_L1D_config.get_line_sz(); input_buffer_capacity = shader_config->n_thread_per_shader*(l1cache_linesize/_flit_size+(int)ceil(8.0f/_flit_size)); } else { input_buffer_capacity = shader_config->n_thread_per_shader*((int)ceil(8.0f/_flit_size)); -- cgit v1.3