From baba81bd9bd5ec5fd07e70b307ccbfeac2d90e0e Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 12 Mar 2018 16:52:26 -0400 Subject: fixibg sectir l1 deadlock bug --- src/gpgpu-sim/gpu-cache.cc | 4 ++-- src/gpgpu-sim/gpu-cache.h | 15 ++++++++++++--- 2 files changed, 14 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 0602e20..8191f62 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -962,7 +962,7 @@ void baseline_cache::send_read_request(new_addr_type addr, new_addr_type block_a m_mshrs.add(mshr_addr,mf); m_extra_mf_fields[mf] = extra_mf_fields(mshr_addr,mf->get_addr(),cache_index, mf->get_data_size(), m_config); mf->set_data_size( m_config.get_atom_sz() ); - mf->set_addr( block_addr ); + mf->set_addr( mshr_addr ); m_miss_queue.push_back(mf); mf->set_status(m_miss_queue_status,time); if(!wa) @@ -1432,7 +1432,7 @@ data_cache::process_tag_probe( bool wr, access_status = (this->*m_wr_hit)( addr, cache_index, mf, time, events, probe_status ); - }else if ( probe_status != RESERVATION_FAIL ) { + }else if ( (probe_status != RESERVATION_FAIL) || (probe_status == RESERVATION_FAIL && m_config.m_write_alloc_policy == NO_WRITE_ALLOCATE) ) { access_status = (this->*m_wr_miss)( addr, cache_index, mf, time, events, probe_status ); diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 0d07878..76b07a2 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -39,7 +39,7 @@ #include enum cache_block_state { - INVALID, + INVALID=0, RESERVED, VALID, MODIFIED @@ -125,6 +125,7 @@ struct cache_block_t { virtual unsigned get_modified_size() = 0; virtual void set_m_readable(bool readable, mem_access_sector_mask_t sector_mask)=0; virtual bool is_readable(mem_access_sector_mask_t sector_mask)=0; + virtual void print_status()=0; virtual ~cache_block_t() {} @@ -144,7 +145,7 @@ struct line_cache_block: public cache_block_t { m_set_modified_on_fill = false; m_readable = true; } - void allocate( new_addr_type tag, new_addr_type block_addr, unsigned time, mem_access_sector_mask_t sector_mask ) + void allocate( new_addr_type tag, new_addr_type block_addr, unsigned time, mem_access_sector_mask_t sector_mask) { m_tag=tag; m_block_addr=block_addr; @@ -220,6 +221,9 @@ struct line_cache_block: public cache_block_t { virtual bool is_readable(mem_access_sector_mask_t sector_mask) { return m_readable; } + virtual void print_status() { + printf("m_block_addr is %u, status = %u\n", m_block_addr, m_status); + } private: @@ -401,6 +405,11 @@ struct sector_cache_block : public cache_block_t { return modified * SECTOR_SIZE; } + virtual void print_status() { + printf("m_block_addr is %u, status = %u %u %u %u\n", m_block_addr, m_status[0], m_status[1], m_status[2], m_status[3]); + } + + private: unsigned m_sector_alloc_time[SECTOR_CHUNCK_SIZE]; unsigned m_last_sector_access_time[SECTOR_CHUNCK_SIZE]; @@ -1030,7 +1039,7 @@ protected: std::string m_name; cache_config &m_config; tag_array* m_tag_array; - mshr_table m_mshrs; + mshr_table m_mshrs; std::list m_miss_queue; enum mem_fetch_status m_miss_queue_status; mem_fetch_interface *m_memport; -- cgit v1.3 From 6dfb3ba656b09acafdb274d7ab04fb081ca06e57 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 8 Nov 2017 20:13:28 -0500 Subject: Fixing the break limit bug --- src/gpgpusim_entrypoint.cc | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index 04845e7..ad4587a 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -91,6 +91,7 @@ void *gpgpu_sim_thread_sequential(void*) pthread_mutex_t g_sim_lock = PTHREAD_MUTEX_INITIALIZER; bool g_sim_active = false; bool g_sim_done = true; +bool break_limit = false; void *gpgpu_sim_thread_concurrent(void*) { @@ -144,11 +145,13 @@ void *gpgpu_sim_thread_concurrent(void*) if(g_the_gpu->cycle_insn_cta_max_hit()){ g_stream_manager->stop_all_running_kernels(); g_sim_done = true; + break_limit = true; } } active=g_the_gpu->active() || !g_stream_manager->empty_protected(); - } while( active ); + + } while( active && !g_sim_done); if(g_debug_execution >= 3) { printf("GPGPU-Sim: ** STOP simulation thread (no work) **\n"); fflush(stdout); @@ -166,6 +169,11 @@ void *gpgpu_sim_thread_concurrent(void*) printf("GPGPU-Sim: *** simulation thread exiting ***\n"); fflush(stdout); } + if(break_limit) { + printf("GPGPU-Sim: ** break due to reaching the maximum cycles (or instructions) **\n"); + exit(1); + } + sem_post(&g_sim_signal_exit); return NULL; } @@ -179,7 +187,7 @@ void synchronize() bool done = false; do { pthread_mutex_lock(&g_sim_lock); - done = g_stream_manager->empty() && !g_sim_active; + done = ( g_stream_manager->empty() && !g_sim_active ) || g_sim_done; pthread_mutex_unlock(&g_sim_lock); } while (!done); printf("GPGPU-Sim: detected inactive GPU simulation thread\n"); -- cgit v1.3 From b4cf66026f66291293c6e11e9c07976f773732fa Mon Sep 17 00:00:00 2001 From: Mengchi Zhang Date: Tue, 3 Oct 2017 11:36:52 -0400 Subject: Add lonestar tick support Signed-off-by: Mengchi Zhang --- cuobjdump_to_ptxplus/ptx_parser.h | 4 ++++ libcuda/cuda_runtime_api.cc | 49 +++++++++++++++++++++++++-------------- src/abstract_hardware_model.h | 10 +++++++- src/cuda-sim/cuda-sim.cc | 5 ++-- src/cuda-sim/ptx.y | 3 ++- src/cuda-sim/ptx_ir.cc | 1 + src/cuda-sim/ptx_ir.h | 7 ++++++ src/cuda-sim/ptx_parser.cc | 4 ++++ src/cuda-sim/ptx_parser.h | 1 + 9 files changed, 62 insertions(+), 22 deletions(-) (limited to 'src') diff --git a/cuobjdump_to_ptxplus/ptx_parser.h b/cuobjdump_to_ptxplus/ptx_parser.h index 418a733..729eaec 100644 --- a/cuobjdump_to_ptxplus/ptx_parser.h +++ b/cuobjdump_to_ptxplus/ptx_parser.h @@ -373,4 +373,8 @@ void func_header_info_int(const char* s, int i) g_headerList->getListEnd().addOperand(buff); } } + +void maxnt_id(int x, int y, int z) { + +} #endif //_PTX_PARSER_H_ diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index d8e7832..4f5e0fb 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -336,23 +336,19 @@ class _cuda_device_id *GPGPUSim_Init() prop->minor = 2; prop->totalGlobalMem = 0x80000000 /* 2 GB */; prop->memPitch = 0; + if(prop->major >= 2) { + prop->maxThreadsPerBlock = 1024; + prop->maxThreadsDim[0] = 1024; + prop->maxThreadsDim[1] = 1024; + } + else + { + prop->maxThreadsPerBlock = 512; + prop->maxThreadsDim[0] = 512; + prop->maxThreadsDim[1] = 512; + } - if(prop->major >= 2) { - prop->maxThreadsPerBlock = 1024; - prop->maxThreadsDim[0] = 1024; - prop->maxThreadsDim[1] = 1024; - } - else - { - prop->maxThreadsPerBlock = 512; - prop->maxThreadsDim[0] = 512; - prop->maxThreadsDim[1] = 512; - } - - prop->maxThreadsDim[2] = 64; - prop->maxGridSize[0] = 0x40000000; - prop->maxGridSize[1] = 0x40000000; - prop->maxGridSize[2] = 0x40000000; + prop->maxThreadsDim[2] = 64; prop->maxGridSize[0] = 0x40000000; prop->maxGridSize[1] = 0x40000000; prop->maxGridSize[2] = 0x40000000; @@ -366,7 +362,7 @@ class _cuda_device_id *GPGPUSim_Init() prop->multiProcessorCount = the_gpu->get_config().num_shader(); #endif #if (CUDART_VERSION >= 4000) - prop->maxThreadsPerMultiProcessor = the_gpu->threads_per_core(); + prop->maxThreadsPerMultiProcessor = the_gpu->threads_per_core(); #endif the_gpu->set_prop(prop); the_device = new _cuda_device_id(the_gpu); @@ -2112,6 +2108,20 @@ cudaError_t CUDARTAPI cudaSetDeviceFlags( int flags ) return g_last_cudaError = cudaErrorUnknown; } +size_t getMaxThreadsPerBlock(struct cudaFuncAttributes *attr) { + _cuda_device_id *dev = GPGPUSim_Init(); + struct cudaDeviceProp prop; + + prop = *dev->get_prop(); + + size_t max = prop.maxThreadsPerBlock; + + if ((prop.regsPerBlock / attr->numRegs) < max) + max = prop.regsPerBlock / attr->numRegs; + + return max; +} + cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, const char *hostFun ) { CUctx_st *context = GPGPUSim_Context(); @@ -2122,7 +2132,10 @@ cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, con attr->constSizeBytes = kinfo->cmem; attr->localSizeBytes = kinfo->lmem; attr->numRegs = kinfo->regs; - attr->maxThreadsPerBlock = 0; // from pragmas? + if(kinfo->maxthreads > 0) + attr->maxThreadsPerBlock = kinfo->maxthreads; + else + attr->maxThreadsPerBlock = getMaxThreadsPerBlock(attr); #if CUDART_VERSION >= 3000 attr->ptxVersion = kinfo->ptx_version; attr->binaryVersion = kinfo->sm_target; diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index cec75f9..1b764e2 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -517,7 +517,14 @@ public: const struct textureReference* get_texref(const std::string &texname) const { std::map::const_iterator t=m_NameToTextureRef.find(texname); - assert( t != m_NameToTextureRef.end() ); + if( t == m_NameToTextureRef.end() ) { + // search for :: prefixed names + std::string temp("::" + texname); + t=m_NameToTextureRef.find(temp); + } + + assert(t != m_NameToTextureRef.end()); + return t->second; } const struct cudaArray* get_texarray( const struct textureReference *texref ) const @@ -568,6 +575,7 @@ struct gpgpu_ptx_sim_info int cmem; int gmem; int regs; + unsigned maxthreads; unsigned ptx_version; unsigned sm_target; }; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 2f166aa..f143d35 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1159,13 +1159,14 @@ void function_info::finalize( memory_space *param_mem ) // copy the parameter over word-by-word so that parameter that crosses a memory page can be copied over //Jin: copy parameter using aligned rules const size_t word_size = 4; - param_address = (param_address + size - 1) / size * size; //aligned with size + //param_address = (param_address + size - 1) / size * size; //aligned with size TODO: align not correct for (size_t idx = 0; idx < size; idx += word_size) { const char *pdata = reinterpret_cast(param_value.pdata) + idx; // cast to char * for ptr arithmetic param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); + param_mem->read(param_address + idx, word_size, &data); } unsigned offset = p.get_offset(); - assert(offset == param_address); + //assert(offset == param_address); param->set_address(param_address); param_address += size; } diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index e00aa4b..c0c58a6 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -228,7 +228,8 @@ function_defn: function_decl { set_symtab($1); func_header(".skip"); } statement block_spec: MAXNTID_DIRECTIVE INT_OPERAND COMMA INT_OPERAND COMMA INT_OPERAND {func_header_info_int(".maxntid", $2); func_header_info_int(",", $4); - func_header_info_int(",", $6); } + func_header_info_int(",", $6); + maxnt_id($2, $4, $6);} | MINNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".minnctapersm", $2); printf("GPGPU-Sim: Warning: .minnctapersm ignored. \n"); } | MAXNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".maxnctapersm", $2); printf("GPGPU-Sim: Warning: .maxnctapersm ignored. \n"); } ; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 8ebdcf8..ee36957 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -222,6 +222,7 @@ bool symbol_table::add_function_decl( const char *name, int entry_point, functio } else { *func_info = new function_info(entry_point); (*func_info)->set_name(name); + (*func_info)->set_maxnt_id(0); m_function_info_lookup[key] = *func_info; } diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 9ad1571..36ef3d5 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1245,6 +1245,7 @@ public: const struct gpgpu_ptx_sim_info* get_kernel_info () const { + assert (m_kernel_info.maxthreads == maxnt_id); return &m_kernel_info; } @@ -1252,6 +1253,8 @@ public: m_kernel_info = info; m_kernel_info.ptx_version = 10*get_ptx_version().ver(); m_kernel_info.sm_target = get_ptx_version().target(); + // THIS DEPENDS ON ptxas being called after the PTX is parsed. + m_kernel_info.maxthreads = maxnt_id; } symbol_table *get_symtab() { @@ -1275,7 +1278,11 @@ public: } bool is_entry_point() const { return m_entry_point; } + void set_maxnt_id(unsigned maxthreads) { maxnt_id = maxthreads;} + unsigned get_maxnt_id() { return maxnt_id;} + private: + unsigned maxnt_id; unsigned m_uid; unsigned m_local_mem_framesize; bool m_entry_point; diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index baa3bcd..e5731a8 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -969,6 +969,10 @@ void target_header3(char* a, char* b, char* c) g_global_symbol_table->set_sm_target(a,b,c); } +void maxnt_id(int x, int y, int z) { + g_func_info->set_maxnt_id(x * y * z); +} + void func_header(const char* a) {} //intentional dummy function void func_header_info(const char* a) {} //intentional dummy function void func_header_info_int(const char* a, int b) {} //intentional dummy function diff --git a/src/cuda-sim/ptx_parser.h b/src/cuda-sim/ptx_parser.h index 32f3903..13042e1 100644 --- a/src/cuda-sim/ptx_parser.h +++ b/src/cuda-sim/ptx_parser.h @@ -93,6 +93,7 @@ void change_double_operand_type( int addr_type ); void change_operand_neg( ); void set_immediate_operand_type( ); void version_header(double a); +void maxnt_id(int x, int y, int z); //Jin: handle instructino group for cdp void start_inst_group(); -- cgit v1.3 From 78a971019b7eac438521c9a77fdf9de30340f29e Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 25 Mar 2018 15:26:38 -0400 Subject: Fixing a bug in mengchi's commit --- src/cuda-sim/cuda-sim.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index f143d35..3d3a820 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1163,7 +1163,6 @@ void function_info::finalize( memory_space *param_mem ) for (size_t idx = 0; idx < size; idx += word_size) { const char *pdata = reinterpret_cast(param_value.pdata) + idx; // cast to char * for ptr arithmetic param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); - param_mem->read(param_address + idx, word_size, &data); } unsigned offset = p.get_offset(); //assert(offset == param_address); -- cgit v1.3 From 4e91a60a48b07f41f4bfb4d59fa2355024a3914b Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 25 Mar 2018 16:51:21 -0400 Subject: Need to make sure we don't kill the L1 too --- configs/Pascal-P100-HBM/gpgpusim.config | 2 ++ configs/Pascal-P102-GDDR5X/gpgpusim.config | 2 ++ configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config | 2 ++ configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 2 ++ src/gpgpu-sim/gpu-sim.cc | 2 +- 5 files changed, 9 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config index 31fbecb..857a0ff 100644 --- a/configs/Pascal-P100-HBM/gpgpusim.config +++ b/configs/Pascal-P100-HBM/gpgpusim.config @@ -55,6 +55,8 @@ # Note: Hashing set index function (H) only applies to a set size of 32 or 64. # Pascal GP100 has 64KB Shared memory -gpgpu_cache:dl1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 -gpgpu_shmem_size 65536 -gpgpu_shmem_size_PrefL1 65536 -gpgpu_shmem_size_PrefShared 65536 diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index 8e1e56f..feb8c0b 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -62,6 +62,8 @@ # Pascal GP102 has 24KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used -gpgpu_cache:dl1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 -gpgpu_shmem_size 49152 -gpgpu_shmem_size_PrefL1 49152 -gpgpu_shmem_size_PrefShared 49152 diff --git a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config index b87d958..a5e6736 100644 --- a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config @@ -55,6 +55,8 @@ # Pascal GP100 has 64KB Shared memory # Pascal GP100 has 48KB L1 cache -gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 65536 -gpgpu_shmem_size_PrefL1 65536 -gpgpu_shmem_size_PrefShared 65536 diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 2df24e1..f78bd02 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -56,6 +56,8 @@ # Pascal GP102 has 64KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used -gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 98304 -gpgpu_shmem_size_PrefL1 98304 -gpgpu_shmem_size_PrefShared 98304 diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 17f1714..bb448b3 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -245,7 +245,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "per-shader L1 data cache config " " {::,:::,::, | none}", "none" ); - option_parser_register(opp, "-gpgpu_cache:dl1PreShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, + option_parser_register(opp, "-gpgpu_cache:dl1PrefShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, "per-shader L1 data cache config " " {::,:::,::, | none}", "none" ); -- cgit v1.3 From 1af82fbe97428654b06b7cd8d40c2d2ce4592aae Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 26 Mar 2018 11:35:25 -0400 Subject: Fixing resources limitation assertion for compute cab 61 --- configs/Pascal-P102-GDDR5X/gpgpusim.config | 1 + src/gpgpu-sim/gpu-sim.cc | 3 +++ src/gpgpu-sim/shader.cc | 4 ++++ src/gpgpu-sim/shader.h | 1 + 4 files changed, 9 insertions(+) (limited to 'src') diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index 0c6c126..b7bcdaf 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -6,6 +6,7 @@ -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 61 +-gpgpu_ignore_resources_limitation 1 # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 17f1714..48af41e 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -268,6 +268,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shader_registers", OPT_UINT32, &gpgpu_shader_registers, "Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)", "8192"); + option_parser_register(opp, "-gpgpu_ignore_resources_limitation", OPT_BOOL, &gpgpu_ignore_resources_limitation, + "gpgpu_ignore_resources_limitation (default 0)", + "0"); option_parser_register(opp, "-gpgpu_shader_cta", OPT_UINT32, &max_cta_per_core, "Maximum number of concurrent CTAs in shader (default 8)", "8"); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index bf482fb..8173191 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -2614,6 +2614,10 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const assert( result <= MAX_CTA_PER_SHADER ); if (result < 1) { printf ("GPGPU-Sim uArch: ERROR ** Kernel requires more resources than shader has.\n"); + if(gpgpu_ignore_resources_limitation) { + printf ("GPGPU-Sim uArch: gpgpu_ignore_resources_limitation is set, ignore the ERROR!\n"); + return 1; + } abort(); } diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 5b41c06..ae22eaa 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1386,6 +1386,7 @@ struct shader_core_config : public core_config unsigned gpgpu_num_reg_banks; bool gpgpu_reg_bank_use_warp_id; bool gpgpu_local_mem_map; + bool gpgpu_ignore_resources_limitation; unsigned max_sp_latency; unsigned max_sfu_latency; -- cgit v1.3 From 67a257442f46a9e8e02f63a9d71fcc7ca54f3f5e Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 28 Mar 2018 14:00:16 -0400 Subject: adding new counters for parition level para and L2 BW --- src/gpgpu-sim/gpu-sim.cc | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'src') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 48af41e..228d4be 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -87,6 +87,12 @@ unsigned long long gpu_tot_sim_cycle = 0; // performance counter for stalls due to congestion. unsigned int gpu_stall_dramfull = 0; unsigned int gpu_stall_icnt2sh = 0; +unsigned long long partiton_reqs_in_parallel = 0; +unsigned long long partiton_reqs_in_parallel_total = 0; +unsigned long long partiton_reqs_in_parallel_util = 0; +unsigned long long partiton_reqs_in_parallel_util_total = 0; +unsigned long long partiton_replys_in_parallel = 0; +unsigned long long partiton_replys_in_parallel_total = 0; /* Clock Domains */ @@ -786,6 +792,9 @@ void gpgpu_sim::init() gpu_sim_insn = 0; last_gpu_sim_insn = 0; m_total_cta_launched=0; + partiton_reqs_in_parallel = 0; + partiton_replys_in_parallel = 0; + partiton_reqs_in_parallel_util = 0; reinit_clock_domains(); set_param_gpgpu_num_shaders(m_config.num_shader()); @@ -822,8 +831,14 @@ void gpgpu_sim::update_stats() { gpu_tot_sim_cycle += gpu_sim_cycle; gpu_tot_sim_insn += gpu_sim_insn; gpu_tot_issued_cta += m_total_cta_launched; + partiton_reqs_in_parallel_total += partiton_reqs_in_parallel; + partiton_replys_in_parallel_total += partiton_replys_in_parallel; + partiton_reqs_in_parallel_util_total += partiton_reqs_in_parallel_util; gpu_sim_cycle = 0; + partiton_reqs_in_parallel = 0; + partiton_replys_in_parallel = 0; + partiton_reqs_in_parallel_util = 0; gpu_sim_insn = 0; m_total_cta_launched = 0; } @@ -1007,6 +1022,19 @@ void gpgpu_sim::gpu_print_stat() printf("gpu_stall_dramfull = %d\n", gpu_stall_dramfull); printf("gpu_stall_icnt2sh = %d\n", gpu_stall_icnt2sh ); + printf("partiton_reqs_in_parallel = %lld\n", partiton_reqs_in_parallel); + printf("partiton_reqs_in_parallel_total = %lld\n", partiton_reqs_in_parallel_total ); + printf("partiton_level_parallism = %12.4f\n", (float)partiton_reqs_in_parallel / gpu_sim_cycle); + printf("partiton_level_parallism_total = %12.4f\n", (float)(partiton_reqs_in_parallel+partiton_reqs_in_parallel_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); + printf("partiton_reqs_in_parallel_util = %lld\n", partiton_reqs_in_parallel_util); + printf("partiton_reqs_in_parallel_util_total = %lld\n", partiton_reqs_in_parallel_util_total ); + printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle); + printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); + printf("partiton_replys_in_parallel = %lld\n", partiton_replys_in_parallel); + printf("partiton_replys_in_parallel_total = %lld\n", partiton_replys_in_parallel_total ); + printf("L2_BW = %12.4f GB/Sec\n", ((float)(partiton_replys_in_parallel * 32) / (gpu_sim_cycle * m_config.icnt_period)) / 1000000000); + printf("L2_BW_total = %12.4f GB/Sec\n", ((float)((partiton_replys_in_parallel+partiton_replys_in_parallel_total) * 32) / ((gpu_tot_sim_cycle+gpu_sim_cycle) * m_config.icnt_period)) / 1000000000 ); + time_t curr_time; time(&curr_time); unsigned long long elapsed_time = MAX( curr_time - g_simulation_starttime, 1 ); @@ -1412,6 +1440,7 @@ void gpgpu_sim::cycle() for (unsigned i=0;in_simt_clusters;i++) m_cluster[i]->icnt_cycle(); } + unsigned partiton_replys_in_parallel_per_cycle = 0; if (clock_mask & ICNT) { // pop from memory controller to interconnect for (unsigned i=0;im_n_mem_sub_partition;i++) { @@ -1424,6 +1453,7 @@ void gpgpu_sim::cycle() mf->set_status(IN_ICNT_TO_SHADER,gpu_sim_cycle+gpu_tot_sim_cycle); ::icnt_push( m_shader_config->mem2device(i), mf->get_tpc(), mf, response_size ); m_memory_sub_partition[i]->pop(); + partiton_replys_in_parallel_per_cycle++; } else { gpu_stall_icnt2sh++; } @@ -1432,6 +1462,7 @@ void gpgpu_sim::cycle() } } } + partiton_replys_in_parallel += partiton_replys_in_parallel_per_cycle; if (clock_mask & DRAM) { for (unsigned i=0;im_n_mem;i++){ @@ -1444,6 +1475,7 @@ void gpgpu_sim::cycle() } // L2 operations follow L2 clock domain + unsigned partiton_reqs_in_parallel_per_cycle = 0; if (clock_mask & L2) { m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].clear(); for (unsigned i=0;im_n_mem_sub_partition;i++) { @@ -1455,11 +1487,15 @@ void gpgpu_sim::cycle() } else { mem_fetch* mf = (mem_fetch*) icnt_pop( m_shader_config->mem2device(i) ); m_memory_sub_partition[i]->push( mf, gpu_sim_cycle + gpu_tot_sim_cycle ); + partiton_reqs_in_parallel_per_cycle++; } m_memory_sub_partition[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle); m_memory_sub_partition[i]->accumulate_L2cache_stats(m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX]); } } + partiton_reqs_in_parallel += partiton_reqs_in_parallel_per_cycle; + if(partiton_reqs_in_parallel_per_cycle > 0) + partiton_reqs_in_parallel_util += partiton_reqs_in_parallel_per_cycle; if (clock_mask & ICNT) { icnt_transfer(); -- cgit v1.3 From 93cdd2e217d7903ccf715a00b6dae8265bb38fca Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 28 Mar 2018 15:22:33 -0400 Subject: adding new stats counter --- src/gpgpu-sim/gpu-sim.cc | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index f216e7c..006d243 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -91,6 +91,8 @@ unsigned long long partiton_reqs_in_parallel = 0; unsigned long long partiton_reqs_in_parallel_total = 0; unsigned long long partiton_reqs_in_parallel_util = 0; unsigned long long partiton_reqs_in_parallel_util_total = 0; +unsigned long long gpu_sim_cycle_parition_util = 0; +unsigned long long gpu_tot_sim_cycle_parition_util = 0; unsigned long long partiton_replys_in_parallel = 0; unsigned long long partiton_replys_in_parallel_total = 0; @@ -795,6 +797,7 @@ void gpgpu_sim::init() partiton_reqs_in_parallel = 0; partiton_replys_in_parallel = 0; partiton_reqs_in_parallel_util = 0; + gpu_sim_cycle_parition_util = 0; reinit_clock_domains(); set_param_gpgpu_num_shaders(m_config.num_shader()); @@ -834,11 +837,14 @@ void gpgpu_sim::update_stats() { partiton_reqs_in_parallel_total += partiton_reqs_in_parallel; partiton_replys_in_parallel_total += partiton_replys_in_parallel; partiton_reqs_in_parallel_util_total += partiton_reqs_in_parallel_util; + gpu_tot_sim_cycle_parition_util += gpu_sim_cycle_parition_util ; gpu_sim_cycle = 0; partiton_reqs_in_parallel = 0; partiton_replys_in_parallel = 0; partiton_reqs_in_parallel_util = 0; + gpu_sim_cycle_parition_util = 0; + gpu_tot_sim_cycle = 0; gpu_sim_insn = 0; m_total_cta_launched = 0; } @@ -1028,8 +1034,10 @@ void gpgpu_sim::gpu_print_stat() printf("partiton_level_parallism_total = %12.4f\n", (float)(partiton_reqs_in_parallel+partiton_reqs_in_parallel_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); printf("partiton_reqs_in_parallel_util = %lld\n", partiton_reqs_in_parallel_util); printf("partiton_reqs_in_parallel_util_total = %lld\n", partiton_reqs_in_parallel_util_total ); - printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle); - printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); + printf("gpu_sim_cycle_parition_util = %lld\n", gpu_sim_cycle_parition_util); + printf("gpu_tot_sim_cycle_parition_util = %lld\n", gpu_tot_sim_cycle_parition_util ); + printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle_parition_util); + printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_sim_cycle_parition_util+gpu_tot_sim_cycle_parition_util) ); printf("partiton_replys_in_parallel = %lld\n", partiton_replys_in_parallel); printf("partiton_replys_in_parallel_total = %lld\n", partiton_replys_in_parallel_total ); printf("L2_BW = %12.4f GB/Sec\n", ((float)(partiton_replys_in_parallel * 32) / (gpu_sim_cycle * m_config.icnt_period)) / 1000000000); @@ -1494,8 +1502,10 @@ void gpgpu_sim::cycle() } } partiton_reqs_in_parallel += partiton_reqs_in_parallel_per_cycle; - if(partiton_reqs_in_parallel_per_cycle > 0) + if(partiton_reqs_in_parallel_per_cycle > 0){ partiton_reqs_in_parallel_util += partiton_reqs_in_parallel_per_cycle; + gpu_sim_cycle_parition_util++; + } if (clock_mask & ICNT) { icnt_transfer(); -- cgit v1.3 From c22eb8a8f6e41921e4e1a5e705cca8d5bbed67e0 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 15:29:46 -0400 Subject: gpuwaatch build does not parallelize nicely without -p --- src/gpuwattch/makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/gpuwattch/makefile b/src/gpuwattch/makefile index ab718cc..354c9ec 100644 --- a/src/gpuwattch/makefile +++ b/src/gpuwattch/makefile @@ -11,10 +11,10 @@ opt: $(TAR).mk obj_opt @$(MAKE) TAG=opt -C . -f $(TAR).mk obj_dbg: - mkdir $@ + mkdir -p $@ obj_opt: - mkdir $@ + mkdir -p $@ depend: @$(MAKE) TAG=opt -C . -f $(TAR).mk depend -- cgit v1.3 From 21ac2041365dc8521a6926244b96e85fd19cc2d3 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 22:52:12 -0400 Subject: Fixing a minor typo in an old config --- src/gpgpu-sim/gpu-sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 58a5d16..d452888 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -223,7 +223,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "per-shader L1 data cache config " " {::,:::,::, | none}", "none" ); - option_parser_register(opp, "-gpgpu_cache:dl1PreShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, + option_parser_register(opp, "-gpgpu_cache:dl1PrefShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, "per-shader L1 data cache config " " {::,:::,::, | none}", "none" ); -- cgit v1.3 From 3b9cc9285b5394320873e42edee03d8f23d6d17e Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Fri, 30 Mar 2018 11:27:57 -0400 Subject: fixing gpu-tot-cycle bug --- src/gpgpu-sim/gpu-sim.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 006d243..7835496 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -844,7 +844,6 @@ void gpgpu_sim::update_stats() { partiton_replys_in_parallel = 0; partiton_reqs_in_parallel_util = 0; gpu_sim_cycle_parition_util = 0; - gpu_tot_sim_cycle = 0; gpu_sim_insn = 0; m_total_cta_launched = 0; } -- cgit v1.3 From 6aba79083ec47a78ad2a9572a03cd52f42141def Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 30 Mar 2018 16:10:27 -0400 Subject: When CDP was added - we started printing garbage stats after every memcpy. I am stopping this by gaurding against it in the same way we do for updating the stat counts (checking if we have executed any cycles before printing). I am not sure what this does to CDP stat prints - as I am not sure what CDP kernels so to sim_cycles.... However EVERY other app except CDP is spewing junk to the output and it really messes up any per-kernel stat collection scripts. --- src/gpgpusim_entrypoint.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index ad4587a..dac9fd8 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -156,8 +156,8 @@ void *gpgpu_sim_thread_concurrent(void*) printf("GPGPU-Sim: ** STOP simulation thread (no work) **\n"); fflush(stdout); } - g_the_gpu->print_stats(); if(sim_cycles) { + g_the_gpu->print_stats(); g_the_gpu->update_stats(); print_simulation_time(); } -- cgit v1.3 From 9b586f9a61cac16b147e6dfea62abecc0a2a8eb7 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 30 Mar 2018 16:20:36 -0400 Subject: Moving the print to avoid spurrious statistics --- src/gpgpusim_entrypoint.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index ad4587a..dac9fd8 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -156,8 +156,8 @@ void *gpgpu_sim_thread_concurrent(void*) printf("GPGPU-Sim: ** STOP simulation thread (no work) **\n"); fflush(stdout); } - g_the_gpu->print_stats(); if(sim_cycles) { + g_the_gpu->print_stats(); g_the_gpu->update_stats(); print_simulation_time(); } -- cgit v1.3 From 89db73061e043c26df22c7f18d9adb106d8078ac Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 31 Mar 2018 17:56:50 -0400 Subject: Getting rid of our constant, annoying prints. Running workloads of any size causes ridiculous output file sizes --- src/cuda-sim/cuda-sim.cc | 2 +- src/gpgpu-sim/gpu-sim.cc | 12 +++++++----- src/gpgpu-sim/shader.cc | 14 ++++++++------ src/trace_streams.tup | 1 + 4 files changed, 17 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index d4ace76..a34b99b 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1408,7 +1408,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) if ( (g_ptx_sim_num_insn % 100000) == 0 ) { dim3 ctaid = get_ctaid(); dim3 tid = get_tid(); - printf("GPGPU-Sim PTX: %u instructions simulated : ctaid=(%u,%u,%u) tid=(%u,%u,%u)\n", + DPRINTF(LIVENESS, "GPGPU-Sim PTX: %u instructions simulated : ctaid=(%u,%u,%u) tid=(%u,%u,%u)\n", g_ptx_sim_num_insn, ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z ); fflush(stdout); } diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index d452888..0ef267d 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -36,6 +36,7 @@ #include "shader.h" +#include "shader_trace.h" #include "dram.h" #include "mem_fetch.h" @@ -1175,8 +1176,8 @@ bool shader_core_ctx::occupy_shader_resource_1block(kernel_info_t & k, bool occu m_occupied_regs += (padded_cta_size * ((kernel_info->regs+3)&~3)); m_occupied_ctas++; - printf("GPGPU-Sim uArch: Shader %d occupied %d threads, %d shared mem, %d registers, %d ctas\n", - m_sid, m_occupied_n_threads, m_occupied_shmem, m_occupied_regs, m_occupied_ctas); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: Occupied %d threads, %d shared mem, %d registers, %d ctas\n", + m_occupied_n_threads, m_occupied_shmem, m_occupied_regs, m_occupied_ctas); } return true; @@ -1301,8 +1302,8 @@ void shader_core_ctx::issue_block2core( kernel_info_t &kernel ) m_n_active_cta++; shader_CTA_count_log(m_sid, 1); - printf("GPGPU-Sim uArch: core:%3d, cta:%2u, start_tid:%4u, end_tid:%4u, initialized @(%lld,%lld)\n", - m_sid, free_cta_hw_id, start_thread, end_thread, gpu_sim_cycle, gpu_tot_sim_cycle ); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: cta:%2u, start_tid:%4u, end_tid:%4u, initialized @(%lld,%lld)\n", + free_cta_hw_id, start_thread, end_thread, gpu_sim_cycle, gpu_tot_sim_cycle ); } @@ -1499,7 +1500,8 @@ void gpgpu_sim::cycle() hrs = elapsed_time/3600 - 24*days; minutes = elapsed_time/60 - 60*(hrs + 24*days); sec = elapsed_time - 60*(minutes + 60*(hrs + 24*days)); - printf("GPGPU-Sim uArch: cycles simulated: %lld inst.: %lld (ipc=%4.1f) sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s", + + DPRINTF(LIVENESS, "GPGPU-Sim uArch: cycles simulated: %lld inst.: %lld (ipc=%4.1f) sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s", gpu_tot_sim_cycle + gpu_sim_cycle, gpu_tot_sim_insn + gpu_sim_insn, (double)gpu_sim_insn/(double)gpu_sim_cycle, (unsigned)((gpu_tot_sim_insn+gpu_sim_insn) / elapsed_time), diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index d17e51d..4640d65 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1969,12 +1969,12 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num, kernel_info_t m_barriers.deallocate_barrier(cta_num); shader_CTA_count_unlog(m_sid, 1); - printf("GPGPU-Sim uArch: Shader %d finished CTA #%d (%lld,%lld), %u CTAs running\n", m_sid, cta_num, gpu_sim_cycle, gpu_tot_sim_cycle, - m_n_active_cta ); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: Finished CTA #%d (%lld,%lld), %u CTAs running\n", + cta_num, gpu_sim_cycle, gpu_tot_sim_cycle, m_n_active_cta); if( m_n_active_cta == 0 ) { - printf("GPGPU-Sim uArch: Shader %u empty (last released kernel %u \'%s\').\n", m_sid, kernel->get_uid(), - kernel->name().c_str() ); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: Empty (last released kernel %u \'%s\').\n", + kernel->get_uid(), kernel->name().c_str()); fflush(stdout); //Shader can only be empty when no more cta are dispatched @@ -1989,8 +1989,10 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num, kernel_info_t kernel->dec_running(); if( !m_gpu->kernel_more_cta_left(kernel) ) { if( !kernel->running() ) { - printf("GPGPU-Sim uArch: GPU detected kernel %u \'%s\' finished on shader %u.\n", kernel->get_uid(), - kernel->name().c_str(), m_sid ); + SHADER_DPRINTF(LIVENESS, + "GPGPU-Sim uArch: GPU detected kernel %u \'%s\' finished on shader %u.\n", kernel->get_uid(), + kernel->name().c_str(), m_sid); + if(m_kernel == kernel) m_kernel = NULL; m_gpu->set_kernel_done( kernel ); diff --git a/src/trace_streams.tup b/src/trace_streams.tup index c41690e..fd68a16 100644 --- a/src/trace_streams.tup +++ b/src/trace_streams.tup @@ -29,5 +29,6 @@ TS_TUP_BEGIN( trace_streams_type ) TS_TUP( WARP_SCHEDULER ), TS_TUP( SCOREBOARD ), TS_TUP( MEMORY_PARTITION_UNIT ), + TS_TUP( LIVENESS ), TS_TUP( NUM_TRACE_STREAMS ) TS_TUP_END( trace_streams_type ) -- cgit v1.3 From 21dae0d20e12018f1a9283596cf79be85b25341c Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 2 Apr 2018 15:25:22 -0400 Subject: print out all the cache stats even if they are zero - makes collection more uniform --- src/gpgpu-sim/gpu-cache.cc | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 8191f62..26a1638 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -658,15 +658,13 @@ void cache_stats::print_stats(FILE *fout, const char *cache_name) const{ std::string m_cache_name = cache_name; for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) { for (unsigned status = 0; status < NUM_CACHE_REQUEST_STATUS; ++status) { - if(m_stats[type][status] > 0){ - fprintf(fout, "\t%s[%s][%s] = %u\n", - m_cache_name.c_str(), - mem_access_type_str((enum mem_access_type)type), - cache_request_status_str((enum cache_request_status)status), - m_stats[type][status]); - if(status != RESERVATION_FAIL) - total_access[type]+= m_stats[type][status]; - } + fprintf(fout, "\t%s[%s][%s] = %u\n", + m_cache_name.c_str(), + mem_access_type_str((enum mem_access_type)type), + cache_request_status_str((enum cache_request_status)status), + m_stats[type][status]); + if(status != RESERVATION_FAIL) + total_access[type]+= m_stats[type][status]; } } for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) { -- cgit v1.3 From d2ae7fb6889cf622673ce1c0d6696d2984963946 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Thu, 5 Apr 2018 11:27:17 -0400 Subject: Nice to know when the simulaton thread actually gets the exit call under normal operation. This helps immensely in a clustered environmrnt where jobs randomly fail --- src/gpgpusim_entrypoint.cc | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index dac9fd8..52e2f5e 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -93,8 +93,15 @@ bool g_sim_active = false; bool g_sim_done = true; bool break_limit = false; +static void termination_callback() +{ + printf("GPGPU-Sim: *** exit detected ***\n"); + fflush(stdout); +} + void *gpgpu_sim_thread_concurrent(void*) { + atexit(termination_callback); // concurrent kernel execution simulation thread do { if(g_debug_execution >= 3) { @@ -165,10 +172,10 @@ void *gpgpu_sim_thread_concurrent(void*) g_sim_active = false; pthread_mutex_unlock(&g_sim_lock); } while( !g_sim_done ); - if(g_debug_execution >= 3) { - printf("GPGPU-Sim: *** simulation thread exiting ***\n"); - fflush(stdout); - } + + printf("GPGPU-Sim: *** simulation thread exiting ***\n"); + fflush(stdout); + if(break_limit) { printf("GPGPU-Sim: ** break due to reaching the maximum cycles (or instructions) **\n"); exit(1); -- cgit v1.3 From f25a04e6a3db604f52d655fa98b99ad8f5343015 Mon Sep 17 00:00:00 2001 From: green349 Date: Wed, 11 Apr 2018 16:15:31 -0400 Subject: Add support for isnan to compile with GCC-4.8.2 --- src/cuda-sim/cuda-math.h | 4 +++- src/cuda-sim/instructions.cc | 9 +++++---- 2 files changed, 8 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/cuda-sim/cuda-math.h b/src/cuda-sim/cuda-math.h index 4721e8a..f88c526 100644 --- a/src/cuda-sim/cuda-math.h +++ b/src/cuda-sim/cuda-math.h @@ -67,6 +67,8 @@ #ifndef CUDA_MATH #define CUDA_MATH +#include + // cuda math implementations #undef max #undef min @@ -321,7 +323,7 @@ float __internal_accurate_fdividef(float a, float b) float __saturatef(float a) { float b; - if (isnan(a)) b = 0.0f; + if (std::isnan(a)) b = 0.0f; else if (a >= 1.0f) b = 1.0f; else if (a <= 0.0f) b = 0.0f; else b = a; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 011c285..e3b8970 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -33,6 +33,7 @@ #include "ptx.tab.h" #include #include +#include #include #include "cuda-math.h" #include "../abstract_hardware_model.h" @@ -1961,7 +1962,7 @@ ptx_reg_t d2d( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, y.f64 = x.f64; break; } - if (isnan(y.f64)) { + if (std::isnan(y.f64)) { y.u64 = 0xfff8000000000000ull; } else if (saturation_mode) { y.f64 = cuda_math::__saturatef(y.f64); @@ -2086,7 +2087,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) } } if ((type == F64_TYPE)||(type == FF64_TYPE)) { - if (isnan(data.f64)) { + if (std::isnan(data.f64)) { data.u64 = 0xfff8000000000000ull; } } @@ -2648,12 +2649,12 @@ void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry bool isNaN(float x) { - return isnan(x); + return std::isnan(x); } bool isNaN(double x) { - return isnan(x); + return std::isnan(x); } void max_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -- cgit v1.3 From 0fed92bcefeffc16822bd07e3b436fcd7e490f57 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 12 Apr 2018 11:49:01 -0400 Subject: fixing FCFS bug --- src/gpgpu-sim/mem_latency_stat.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc index 35d6d84..8fdbe06 100644 --- a/src/gpgpu-sim/mem_latency_stat.cc +++ b/src/gpgpu-sim/mem_latency_stat.cc @@ -230,6 +230,7 @@ void memory_stats_t::memlatstat_print( unsigned n_mem, unsigned gpu_mem_n_bk ) if (num_mfs) { printf("averagemflatency = %lld \n", mf_total_lat/num_mfs); printf("avg_icnt2mem_latency = %lld \n", tot_icnt2mem_latency/num_mfs); + if(tot_mrq_num) printf("avg_mrq_latency = %lld \n", tot_mrq_latency/tot_mrq_num); printf("avg_icnt2sh_latency = %lld \n", tot_icnt2sh_latency/num_mfs); } -- cgit v1.3 From 9217cff18ab7608ee21ad48061be8f6febf88780 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 12 Apr 2018 13:05:04 -0400 Subject: adding sime spaces --- src/gpgpu-sim/mem_latency_stat.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc index 8fdbe06..c5452b9 100644 --- a/src/gpgpu-sim/mem_latency_stat.cc +++ b/src/gpgpu-sim/mem_latency_stat.cc @@ -231,7 +231,8 @@ void memory_stats_t::memlatstat_print( unsigned n_mem, unsigned gpu_mem_n_bk ) printf("averagemflatency = %lld \n", mf_total_lat/num_mfs); printf("avg_icnt2mem_latency = %lld \n", tot_icnt2mem_latency/num_mfs); if(tot_mrq_num) - printf("avg_mrq_latency = %lld \n", tot_mrq_latency/tot_mrq_num); + printf("avg_mrq_latency = %lld \n", tot_mrq_latency/tot_mrq_num); + printf("avg_icnt2sh_latency = %lld \n", tot_icnt2sh_latency/num_mfs); } printf("mrq_lat_table:"); -- cgit v1.3 From 1e1c08286a505418d0e3ad1ee819e15881e9cb43 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Fri, 15 Jun 2018 16:46:14 -0400 Subject: memory partition indexing --- configs/4.x-cfgs/SM6_P100/gpgpusim.config | 1 + src/gpgpu-sim/addrdec.cc | 48 +++++++++++++++++++++++++++++++ src/gpgpu-sim/addrdec.h | 8 ++++++ src/gpgpu-sim/dram.cc | 2 +- src/gpgpu-sim/gpu-cache.cc | 36 ++++++++++++++++++++++- src/gpgpu-sim/gpu-cache.h | 7 +++-- 6 files changed, 98 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/configs/4.x-cfgs/SM6_P100/gpgpusim.config b/configs/4.x-cfgs/SM6_P100/gpgpusim.config index 9a7259e..a43c0bb 100644 --- a/configs/4.x-cfgs/SM6_P100/gpgpusim.config +++ b/configs/4.x-cfgs/SM6_P100/gpgpusim.config @@ -69,6 +69,7 @@ -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 -perf_sim_memcpy 0 +-memory_partition_indexing 2 # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc index 422576d..cfd90ec 100644 --- a/src/gpgpu-sim/addrdec.cc +++ b/src/gpgpu-sim/addrdec.cc @@ -62,6 +62,9 @@ void linear_to_raw_address_translation::addrdec_setoption(option_parser_t opp) option_parser_register(opp, "-gpgpu_mem_address_mask", OPT_INT32, &gpgpu_mem_address_mask, "0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits", "0"); + option_parser_register(opp, "-memory_partition_indexing", OPT_UINT32, &memory_partition_indexing, + "0 = no indexing, 1 = bitwise xoring, 2 = IPoly, 3 = custom indexing", + "0"); } new_addr_type linear_to_raw_address_translation::partition_address( new_addr_type addr ) const @@ -103,6 +106,51 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_ tlx->burst= addrdec_packbits(addrdec_mask[BURST], rest_of_addr, addrdec_mkhigh[BURST], addrdec_mklow[BURST]); } + switch(memory_partition_indexing){ + case CONSECUTIVE: + //Do nothing + break; + case BITWISE_PERMUTATION: + assert(!gap); + tlx->chip = (tlx->chip) ^ (tlx->row & (m_n_channel-1)); + assert(tlx->chip < m_n_channel); + break; + case IPOLY: + /* + * Set Indexing function from "Pseudo-randomly interleaved memory." + * Rau, B. R et al. + * ISCA 1991 + * + * equations are adopted from: + * "Sacat: streaming-aware conflict-avoiding thrashing-resistant gpgpu cache management scheme." + * Khairy et al. + * IEEE TPDS 2017. + */ + if(m_n_channel == 32) { + std::bitset<64> a(tlx->row); + std::bitset<5> chip(tlx->chip); + chip[0] = a[13]^a[12]^a[11]^a[10]^a[9]^a[6]^a[5]^a[3]^a[0]^chip[0]; + chip[1] = a[14]^a[13]^a[12]^a[11]^a[10]^a[7]^a[6]^a[4]^a[1]^chip[1]; + chip[2] = a[14]^a[10]^a[9]^a[8]^a[7]^a[6]^a[3]^a[2]^a[0]^chip[2]; + chip[3] = a[11]^a[10]^a[9]^a[8]^a[7]^a[4]^a[3]^a[1]^chip[3]; + chip[4] = a[12]^a[11]^a[10]^a[9]^a[8]^a[5]^a[4]^a[2]^chip[4]; + tlx->chip = chip.to_ulong(); + + } + else{ /* Else incorrect number of channels for the hashing function */ + assert("\nGPGPU-Sim memory_partition_indexing error: The number of channels should be " + "32 for the hashing IPOLY index function.\n" && 0); + } + assert(tlx->chip < m_n_channel); + break; + case CUSTOM: + /* No custom set function implemented */ + break; + default: + assert("\nUndefined set index function.\n" && 0); + break; + } + // combine the chip address and the lower bits of DRAM bank address to form the subpartition ID unsigned sub_partition_addr_mask = m_n_sub_partition_in_channel - 1; tlx->sub_partition = tlx->chip * m_n_sub_partition_in_channel diff --git a/src/gpgpu-sim/addrdec.h b/src/gpgpu-sim/addrdec.h index fd9af8d..a18ff63 100644 --- a/src/gpgpu-sim/addrdec.h +++ b/src/gpgpu-sim/addrdec.h @@ -35,6 +35,13 @@ #include "../abstract_hardware_model.h" +enum partition_index_function{ + CONSECUTIVE = 0, + BITWISE_PERMUTATION, + IPOLY, + CUSTOM +}; + struct addrdec_t { void print( FILE *fp ) const; @@ -72,6 +79,7 @@ private: const char *addrdec_option; int gpgpu_mem_address_mask; + partition_index_function memory_partition_indexing; bool run_test; int ADDR_CHIP_S; diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index a57508c..92aa819 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -204,7 +204,7 @@ dram_req_t::dram_req_t( class mem_fetch *mf, unsigned banks, unsigned dram_bnk_i } else if(dram_bnk_indexing_policy == 1) { int lbank = log2(banks); - bk = tlx.bk ^ (((1< a(addr); + std::bitset<6> index; + index[0] = a[25]^a[24]^a[23]^a[22]^a[21]^a[18]^a[17]^a[15]^a[12]^a[7]; //10 + index[1] = a[26]^a[25]^a[24]^a[23]^a[22]^a[19]^a[18]^a[16]^a[13]^a[8]; //10 + index[2] = a[26]^a[22]^a[21]^a[20]^a[19]^a[18]^a[15]^a[14]^a[12]^a[9]; //10 + index[3] = a[23]^a[22]^a[21]^a[20]^a[19]^a[16]^a[15]^a[13]^a[10]; //9 + index[4] = a[24]^a[23]^a[22]^a[21]^a[20]^a[17]^a[16]^a[14]^a[11]; //9 + + if(m_nset == 64) + index[5] = a[12]; + + set_index = index.to_ulong(); + + }else{ /* Else incorrect number of sets for the hashing function */ + assert("\nGPGPU-Sim cache configuration error: The number of sets should be " + "32 or 64 for the hashing set index function.\n" && 0); + } + break; + case CUSTOM_SET_FUNCTION: /* No custom set function implemented */ break; @@ -104,6 +134,10 @@ unsigned l1d_cache_config::set_index(new_addr_type addr) const{ case LINEAR_SET_FUNCTION: set_index = (addr >> m_line_sz_log2) & (m_nset-1); break; + + default: + assert("\nUndefined set index function.\n" && 0); + break; } // Linear function selected or custom set index function not implemented diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 76b07a2..d2b7757 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -464,8 +464,10 @@ enum mshr_config_t { }; enum set_index_function{ - FERMI_HASH_SET_FUNCTION = 0, - LINEAR_SET_FUNCTION, + LINEAR_SET_FUNCTION = 0, + BITWISE_XORING_FUNCTION, + HASH_IPOLY_FUNCTION, + FERMI_HASH_SET_FUNCTION, CUSTOM_SET_FUNCTION }; @@ -587,6 +589,7 @@ public: switch(sif){ case 'H': m_set_index_function = FERMI_HASH_SET_FUNCTION; break; + case 'P': m_set_index_function = HASH_IPOLY_FUNCTION; break; case 'C': m_set_index_function = CUSTOM_SET_FUNCTION; break; case 'L': m_set_index_function = LINEAR_SET_FUNCTION; break; default: exit_parse_error(); -- cgit v1.3