From b4cf66026f66291293c6e11e9c07976f773732fa Mon Sep 17 00:00:00 2001 From: Mengchi Zhang Date: Tue, 3 Oct 2017 11:36:52 -0400 Subject: Add lonestar tick support Signed-off-by: Mengchi Zhang --- src/abstract_hardware_model.h | 10 +++++++++- src/cuda-sim/cuda-sim.cc | 5 +++-- src/cuda-sim/ptx.y | 3 ++- src/cuda-sim/ptx_ir.cc | 1 + src/cuda-sim/ptx_ir.h | 7 +++++++ src/cuda-sim/ptx_parser.cc | 4 ++++ src/cuda-sim/ptx_parser.h | 1 + 7 files changed, 27 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index cec75f9..1b764e2 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -517,7 +517,14 @@ public: const struct textureReference* get_texref(const std::string &texname) const { std::map::const_iterator t=m_NameToTextureRef.find(texname); - assert( t != m_NameToTextureRef.end() ); + if( t == m_NameToTextureRef.end() ) { + // search for :: prefixed names + std::string temp("::" + texname); + t=m_NameToTextureRef.find(temp); + } + + assert(t != m_NameToTextureRef.end()); + return t->second; } const struct cudaArray* get_texarray( const struct textureReference *texref ) const @@ -568,6 +575,7 @@ struct gpgpu_ptx_sim_info int cmem; int gmem; int regs; + unsigned maxthreads; unsigned ptx_version; unsigned sm_target; }; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 2f166aa..f143d35 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1159,13 +1159,14 @@ void function_info::finalize( memory_space *param_mem ) // copy the parameter over word-by-word so that parameter that crosses a memory page can be copied over //Jin: copy parameter using aligned rules const size_t word_size = 4; - param_address = (param_address + size - 1) / size * size; //aligned with size + //param_address = (param_address + size - 1) / size * size; //aligned with size TODO: align not correct for (size_t idx = 0; idx < size; idx += word_size) { const char *pdata = reinterpret_cast(param_value.pdata) + idx; // cast to char * for ptr arithmetic param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); + param_mem->read(param_address + idx, word_size, &data); } unsigned offset = p.get_offset(); - assert(offset == param_address); + //assert(offset == param_address); param->set_address(param_address); param_address += size; } diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index e00aa4b..c0c58a6 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -228,7 +228,8 @@ function_defn: function_decl { set_symtab($1); func_header(".skip"); } statement block_spec: MAXNTID_DIRECTIVE INT_OPERAND COMMA INT_OPERAND COMMA INT_OPERAND {func_header_info_int(".maxntid", $2); func_header_info_int(",", $4); - func_header_info_int(",", $6); } + func_header_info_int(",", $6); + maxnt_id($2, $4, $6);} | MINNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".minnctapersm", $2); printf("GPGPU-Sim: Warning: .minnctapersm ignored. \n"); } | MAXNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".maxnctapersm", $2); printf("GPGPU-Sim: Warning: .maxnctapersm ignored. \n"); } ; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 8ebdcf8..ee36957 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -222,6 +222,7 @@ bool symbol_table::add_function_decl( const char *name, int entry_point, functio } else { *func_info = new function_info(entry_point); (*func_info)->set_name(name); + (*func_info)->set_maxnt_id(0); m_function_info_lookup[key] = *func_info; } diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 9ad1571..36ef3d5 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1245,6 +1245,7 @@ public: const struct gpgpu_ptx_sim_info* get_kernel_info () const { + assert (m_kernel_info.maxthreads == maxnt_id); return &m_kernel_info; } @@ -1252,6 +1253,8 @@ public: m_kernel_info = info; m_kernel_info.ptx_version = 10*get_ptx_version().ver(); m_kernel_info.sm_target = get_ptx_version().target(); + // THIS DEPENDS ON ptxas being called after the PTX is parsed. + m_kernel_info.maxthreads = maxnt_id; } symbol_table *get_symtab() { @@ -1275,7 +1278,11 @@ public: } bool is_entry_point() const { return m_entry_point; } + void set_maxnt_id(unsigned maxthreads) { maxnt_id = maxthreads;} + unsigned get_maxnt_id() { return maxnt_id;} + private: + unsigned maxnt_id; unsigned m_uid; unsigned m_local_mem_framesize; bool m_entry_point; diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index baa3bcd..e5731a8 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -969,6 +969,10 @@ void target_header3(char* a, char* b, char* c) g_global_symbol_table->set_sm_target(a,b,c); } +void maxnt_id(int x, int y, int z) { + g_func_info->set_maxnt_id(x * y * z); +} + void func_header(const char* a) {} //intentional dummy function void func_header_info(const char* a) {} //intentional dummy function void func_header_info_int(const char* a, int b) {} //intentional dummy function diff --git a/src/cuda-sim/ptx_parser.h b/src/cuda-sim/ptx_parser.h index 32f3903..13042e1 100644 --- a/src/cuda-sim/ptx_parser.h +++ b/src/cuda-sim/ptx_parser.h @@ -93,6 +93,7 @@ void change_double_operand_type( int addr_type ); void change_operand_neg( ); void set_immediate_operand_type( ); void version_header(double a); +void maxnt_id(int x, int y, int z); //Jin: handle instructino group for cdp void start_inst_group(); -- cgit v1.3 From 78a971019b7eac438521c9a77fdf9de30340f29e Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 25 Mar 2018 15:26:38 -0400 Subject: Fixing a bug in mengchi's commit --- src/cuda-sim/cuda-sim.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index f143d35..3d3a820 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1163,7 +1163,6 @@ void function_info::finalize( memory_space *param_mem ) for (size_t idx = 0; idx < size; idx += word_size) { const char *pdata = reinterpret_cast(param_value.pdata) + idx; // cast to char * for ptr arithmetic param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); - param_mem->read(param_address + idx, word_size, &data); } unsigned offset = p.get_offset(); //assert(offset == param_address); -- cgit v1.3 From 4e91a60a48b07f41f4bfb4d59fa2355024a3914b Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 25 Mar 2018 16:51:21 -0400 Subject: Need to make sure we don't kill the L1 too --- configs/Pascal-P100-HBM/gpgpusim.config | 2 ++ configs/Pascal-P102-GDDR5X/gpgpusim.config | 2 ++ configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config | 2 ++ configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 2 ++ src/gpgpu-sim/gpu-sim.cc | 2 +- 5 files changed, 9 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config index 31fbecb..857a0ff 100644 --- a/configs/Pascal-P100-HBM/gpgpusim.config +++ b/configs/Pascal-P100-HBM/gpgpusim.config @@ -55,6 +55,8 @@ # Note: Hashing set index function (H) only applies to a set size of 32 or 64. # Pascal GP100 has 64KB Shared memory -gpgpu_cache:dl1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 -gpgpu_shmem_size 65536 -gpgpu_shmem_size_PrefL1 65536 -gpgpu_shmem_size_PrefShared 65536 diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index 8e1e56f..feb8c0b 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -62,6 +62,8 @@ # Pascal GP102 has 24KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used -gpgpu_cache:dl1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 -gpgpu_shmem_size 49152 -gpgpu_shmem_size_PrefL1 49152 -gpgpu_shmem_size_PrefShared 49152 diff --git a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config index b87d958..a5e6736 100644 --- a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config @@ -55,6 +55,8 @@ # Pascal GP100 has 64KB Shared memory # Pascal GP100 has 48KB L1 cache -gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 65536 -gpgpu_shmem_size_PrefL1 65536 -gpgpu_shmem_size_PrefShared 65536 diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 2df24e1..f78bd02 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -56,6 +56,8 @@ # Pascal GP102 has 64KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used -gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 98304 -gpgpu_shmem_size_PrefL1 98304 -gpgpu_shmem_size_PrefShared 98304 diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 17f1714..bb448b3 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -245,7 +245,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "per-shader L1 data cache config " " {::,:::,::, | none}", "none" ); - option_parser_register(opp, "-gpgpu_cache:dl1PreShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, + option_parser_register(opp, "-gpgpu_cache:dl1PrefShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, "per-shader L1 data cache config " " {::,:::,::, | none}", "none" ); -- cgit v1.3 From 1af82fbe97428654b06b7cd8d40c2d2ce4592aae Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 26 Mar 2018 11:35:25 -0400 Subject: Fixing resources limitation assertion for compute cab 61 --- configs/Pascal-P102-GDDR5X/gpgpusim.config | 1 + src/gpgpu-sim/gpu-sim.cc | 3 +++ src/gpgpu-sim/shader.cc | 4 ++++ src/gpgpu-sim/shader.h | 1 + 4 files changed, 9 insertions(+) (limited to 'src') diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index 0c6c126..b7bcdaf 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -6,6 +6,7 @@ -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 61 +-gpgpu_ignore_resources_limitation 1 # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 17f1714..48af41e 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -268,6 +268,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shader_registers", OPT_UINT32, &gpgpu_shader_registers, "Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)", "8192"); + option_parser_register(opp, "-gpgpu_ignore_resources_limitation", OPT_BOOL, &gpgpu_ignore_resources_limitation, + "gpgpu_ignore_resources_limitation (default 0)", + "0"); option_parser_register(opp, "-gpgpu_shader_cta", OPT_UINT32, &max_cta_per_core, "Maximum number of concurrent CTAs in shader (default 8)", "8"); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index bf482fb..8173191 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -2614,6 +2614,10 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const assert( result <= MAX_CTA_PER_SHADER ); if (result < 1) { printf ("GPGPU-Sim uArch: ERROR ** Kernel requires more resources than shader has.\n"); + if(gpgpu_ignore_resources_limitation) { + printf ("GPGPU-Sim uArch: gpgpu_ignore_resources_limitation is set, ignore the ERROR!\n"); + return 1; + } abort(); } diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 5b41c06..ae22eaa 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1386,6 +1386,7 @@ struct shader_core_config : public core_config unsigned gpgpu_num_reg_banks; bool gpgpu_reg_bank_use_warp_id; bool gpgpu_local_mem_map; + bool gpgpu_ignore_resources_limitation; unsigned max_sp_latency; unsigned max_sfu_latency; -- cgit v1.3