# functional simulator specification
-gpgpu_ptx_instruction_classification 0
-gpgpu_ptx_sim_mode 0
-gpgpu_ptx_force_max_capability 15

# high level architecture configuration
-gpgpu_n_clusters 15
-gpgpu_n_cores_per_cluster 1
-gpgpu_n_mem 6

# Fermi
-gpgpu_clock_domains 700.0:700.0:700.0:3696.0

# shader core pipeline config
-gpgpu_shader_registers 32768

# ask wilson about the next two lines
-gpgpu_shader_core_pipeline 1024:32:32 
-gpgpu_shader_cta 16
-gpgpu_simd_model 1 


# In Fermi, the cache and shared memory could be configured to 16kb:48kb or 48kb:16kb
# <nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>
# mysteriously gives much better correlation (and faster runs) than a configured cache
#-gpgpu_cache:dl1 none
-gpgpu_cache:dl1  32:128:4:L:R:f,A:32:8,8
-gpgpu_shmem_size 49152
#-gpgpu_cache:dl1  64:128:6:L:R:f,A:32:8,8
#-gpgpu_shmem_size 16384

# 256 sets, each 512 bits 6-way, this gives 786KB L2 cache
# this entry gives slightly worse correlation that the quadro config
-gpgpu_cache:dl2 256:512:6:L:R:m,A:32:4,4
#-gpgpu_cache:dl2 64:32:8:L:R:m,A:16:4,4
#-gpgpu_cache:dl2_texture_only

-gpgpu_cache:il1 4:128:4:L:R:f,A:2:32,4
-gpgpu_tex_cache:l1 4:128:24:L:R:m,F:128:4,128:2
-gpgpu_const_cache:l1 64:64:2:L:R:f,A:2:32,4
#-gpgpu_tex_cache:l1 none
#-gpgpu_const_cache:l1 none

-gpgpu_num_reg_banks 16

-gpgpu_shmem_warp_parts 2

-gpgpu_max_insn_issue_per_warp 1

# interconnection
-network_mode 1 
-inter_config_file icnt_config_quadro_islip.txt 

# dram model config
-gpgpu_dram_scheduler 1
-gpgpu_dram_sched_queue_size 16
-gpgpu_n_mem_per_ctrlr 2

# for Fermi, bus width is 384bits, this is 24 bytes *2 because of double data rate
# try if making the buswidth smaller affects the correlation, should try the memory frequency too
-gpgpu_dram_buswidth 24 
-gpgpu_dram_burst_length 4
-gpgpu_mem_address_mask 1
-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS

# ANDREW
# GDDR5 timing from hynix H5GQ1H24AFR
# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR}
# CL and WL need to be figured out accurately
# in the GDDR5 datasheet WL= min 3, max 7
# I couldn't find tCDLR in the datasheet either, what does it mean? ask wilson may be
# This configuration turns out to decrease the cpi correlation by about .03% for Fermi probably increases clk correlation
-gpgpu_dram_timing_opt 16:2:5:12:28:12:35:10:7:6:12

# GDDR3
#-gpgpu_dram_timing_opt 8:2:8:12:25:10:35:10:7:6:11

# Fermi has two schedulers per core
-gpgpu_num_sched_per_core 2



# stat collection
-gpgpu_memlatency_stat 14 
-gpgpu_runtime_stat 500
-enable_ptx_file_line_stats 1

# enable SASS execution
#-gpgpu_ptx_convert_to_ptxplus 1
#-gpgpu_ptx_save_converted_ptxplus 1

# enable operand collector 
-gpgpu_operand_collector_num_units_sp 6
-gpgpu_operand_collector_num_units_sfu 8

-visualizer_enabled 0