# functional simulator specification
-gpgpu_ptx_instruction_classification 0
-gpgpu_ptx_sim_mode 0
-gpgpu_ptx_force_max_capability 20 

# high level architecture configuration
-gpgpu_n_clusters 15
-gpgpu_n_cores_per_cluster 1
-gpgpu_n_mem 6

# Fermi clock domains
#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
-gpgpu_clock_domains 700.0:1400.0:700.0:1848.0

# shader core pipeline config
-gpgpu_shader_registers 32768

# This implies a maximum of 48 warps/SM
-gpgpu_shader_core_pipeline 1536:32 
-gpgpu_shader_cta 8
-gpgpu_simd_model 1 

# Pipeline widths and number of FUs
# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
-gpgpu_pipeline_widths 2,1,1,2,1,1,2
-gpgpu_num_sp_units 2
-gpgpu_num_sfu_units 1

# Instruction latencies and initiation intervals
# "ADD,MAX,MUL,MAD,DIV"
-ptx_opcode_latency_int 4,13,4,5,145
-ptx_opcode_initiation_int 1,2,2,1,8
-ptx_opcode_latency_fp 4,13,4,5,39
-ptx_opcode_initiation_fp 1,2,1,1,4
-ptx_opcode_latency_dp 8,19,8,8,330
-ptx_opcode_initiation_dp 8,16,8,8,130

# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
# <nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>
-gpgpu_cache:dl1  32:128:4:L:R:m,A:32:8,8
-gpgpu_shmem_size 49152

# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
#-gpgpu_cache:dl1  64:128:6:L:R:f,A:32:8,8
#-gpgpu_shmem_size 16384

# 64 sets, each 256 bytes 8-way for each memory partition. This gives 786KB L2 cache
-gpgpu_cache:dl2 64:256:8:L:R:m,A:32:4,4
-gpgpu_cache:dl2_texture_only 0 

-gpgpu_cache:il1 4:128:4:L:R:f,A:2:32,4
-gpgpu_tex_cache:l1 4:128:24:L:R:m,F:128:4,128:2
-gpgpu_const_cache:l1 64:64:2:L:R:f,A:2:32,4

-gpgpu_num_reg_banks 16

-gpgpu_shmem_warp_parts 1

-gpgpu_max_insn_issue_per_warp 1

# interconnection
-network_mode 1 
-inter_config_file icnt_config_fermi_islip.txt 

# memory partition latency config 
-rop_latency 120
-dram_latency 100

# dram model config
-gpgpu_dram_scheduler 1
-gpgpu_dram_sched_queue_size 16

# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
-gpgpu_n_mem_per_ctrlr 2
-gpgpu_dram_buswidth 4
-gpgpu_dram_burst_length 4
-gpgpu_mem_address_mask 1
-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS

# GDDR5 timing from hynix H5GQ1H24AFR
# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
-gpgpu_dram_timing_opt 16:2:5:12:28:12:35:10:7:6:12:4:3:2

# GDDR3
#-gpgpu_dram_timing_opt 8:2:8:12:25:10:35:10:7:6:11

# Fermi has two schedulers per core
-gpgpu_num_sched_per_core 2

# stat collection
-gpgpu_memlatency_stat 14 
-gpgpu_runtime_stat 500
-enable_ptx_file_line_stats 1

# Using cuobjdump to extract ptx/SASS
-gpgpu_ptx_use_cuobjdump 0

# SASS execution (only supported with CUDA >= 4.0)
-gpgpu_ptx_convert_to_ptxplus 0
-gpgpu_ptx_save_converted_ptxplus 0

# enable operand collector 
-gpgpu_operand_collector_num_units_sp 6
-gpgpu_operand_collector_num_units_sfu 8
-gpgpu_operand_collector_num_in_ports_sp 2
-gpgpu_operand_collector_num_out_ports_sp 2
-visualizer_enabled 0