# functional simulator specification
-gpgpu_ptx_instruction_classification 0
-gpgpu_ptx_sim_mode 0
-gpgpu_cuda_sim

# high level architecture configuration
-gpgpu_n_shader 30 -gpgpu_n_mem 8 -gpgpu_clock_domains 325.0:650.0:650.0:800.0 
-gpgpu_spread_blocks_across_cores

# shader core pipeline config
-gpgpu_shader_registers 16384
-gpgpu_shader_core_pipeline 1024:32:32 
-gpgpu_shader_cta 8
-gpgpu_pre_mem_stages 1
-gpgpu_pdom_sched_type 8
-gpgpu_simd_model 1 

# memory stage behaviour
-gpgpu_no_dl1 1 
-gpgpu_shmem_bkconflict 1
-gpgpu_cache_bkconflict 1
-gpgpu_n_cache_bank 1
-gpgpu_shmem_pipe_speedup 2
-gpgpu_shmem_port_per_bank 2
-gpgpu_cache_port_per_bank 2
-gpgpu_const_port_per_bank 2
-gpgpu_interwarp_mshr_merge 6
-gpgpu_cache:dl1 128:64:4:L 
-gpgpu_tex_cache:l1 64:64:2:L -gpgpu_const_cache:l1 64:64:2:L 

# interconnection
-network_mode 1 
-inter_config_file icnt_config_quadro_islip.txt 
-gpu_concentration 3 

# dram model config
-gpgpu_dram_scheduler 1
-gpgpu_dram_sched_queue_size 32
-gpgpu_n_mem_per_ctrlr 2
-gpgpu_dram_buswidth 4 
-gpgpu_dram_burst_length 4
-gpgpu_partial_write_mask 1
-gpgpu_mem_address_mask 1
-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tWTR}
-gpgpu_dram_timing_opt 8:2:8:12:25:10:35:10:7:6

# stat collection
-gpgpu_memlatency_stat 14 
-gpgpu_runtime_stat 1000
-enable_ptx_file_line_stats 1