# This config models the Turing RTX 2060 # For more info about turing architecture: # 1- https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf # 2- "RTX on—The NVIDIA Turing GPU", IEEE MICRO 2020 # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 75 # Device Limits -gpgpu_stack_size_limit 1024 -gpgpu_heap_size_limit 8388608 -gpgpu_runtime_sync_depth_limit 2 -gpgpu_runtime_pending_launch_count_limit 2048 -gpgpu_kernel_launch_latency 5000 # Compute Capability -gpgpu_compute_capability_major 7 -gpgpu_compute_capability_minor 5 # PTX execution-driven -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 # high level architecture configuration -gpgpu_n_clusters 30 -gpgpu_n_cores_per_cluster 1 -gpgpu_n_mem 12 -gpgpu_n_sub_partition_per_mchannel 2 # volta clock domains #-gpgpu_clock_domains ::: -gpgpu_clock_domains 1365.0:1365.0:1365.0:3500.0 # boost mode # -gpgpu_clock_domains 1680.0:1680.0:1680.0:3500.0 # shader core pipeline config -gpgpu_shader_registers 65536 -gpgpu_registers_per_block 65536 -gpgpu_occupancy_sm_number 75 # This implies a maximum of 32 warps/SM -gpgpu_shader_core_pipeline 1024:32 -gpgpu_shader_cta 32 -gpgpu_simd_model 1 # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE ## Turing has 4 SP SIMD units, 4 INT units, 4 SFU units, 8 Tensor core units ## We need to scale the number of pipeline registers to be equal to the number of SP units -gpgpu_pipeline_widths 4,0,4,4,4,4,0,4,4,4,8,4,4 -gpgpu_num_sp_units 4 -gpgpu_num_sfu_units 4 -gpgpu_num_int_units 4 -gpgpu_tensor_core_avail 1 -gpgpu_num_tensor_core_units 4 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" # All Div operations are executed on SFU unit -ptx_opcode_latency_int 4,13,4,5,145,32 -ptx_opcode_initiation_int 2,2,2,2,8,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 2,2,2,2,4 -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 4,4,4,4,130 -ptx_opcode_latency_sfu 100 -ptx_opcode_initiation_sfu 8 -ptx_opcode_latency_tesnor 64 -ptx_opcode_initiation_tensor 64 # Turing has four schedulers per core -gpgpu_num_sched_per_core 4 # Greedy then oldest scheduler -gpgpu_scheduler gto ## In Turing, a warp scheduler can issue 1 inst per cycle -gpgpu_max_insn_issue_per_warp 1 -gpgpu_dual_issue_diff_exec_units 1 # shared memory bankconflict detection -gpgpu_shmem_num_banks 32 -gpgpu_shmem_limited_broadcast 0 -gpgpu_shmem_warp_parts 1 -gpgpu_coalesce_arch 75 # Trung has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated -gpgpu_sub_core_model 1 # disable specialized operand collectors and use generic operand collectors instead -gpgpu_enable_specialized_operand_collector 0 -gpgpu_operand_collector_num_units_gen 8 -gpgpu_operand_collector_num_in_ports_gen 8 -gpgpu_operand_collector_num_out_ports_gen 8 # turing has 8 banks dual-port, 4 schedulers, two banks per scheduler # we increase #banks to 16 to mitigate the effect of Regisrer File Cache (RFC) which we do not implement in the current version -gpgpu_num_reg_banks 16 -gpgpu_reg_file_port_throughput 2 # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo -gpgpu_adaptive_cache_config 1 -gpgpu_shmem_option 32,64 -gpgpu_unified_l1d_size 96 # L1 cache configuration -gpgpu_l1_banks 4 -gpgpu_cache:dl1 S:4:128:64,L:T:m:L:L,A:512:8,16:0,32 -gpgpu_l1_cache_write_ratio 25 -gpgpu_l1_latency 20 -gpgpu_gmem_skip_L1D 0 -gpgpu_n_cluster_ejection_buffer_size 32 -gpgpu_flush_l1_cache 1 # shared memory configuration -gpgpu_shmem_size 65536 -gpgpu_shmem_sizeDefault 65536 -gpgpu_shmem_per_block 65536 -gpgpu_smem_latency 20 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives us 3MB L2 cache -gpgpu_cache:dl2 S:64:128:16,L:B:m:L:P,A:192:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 -gpgpu_perf_sim_memcpy 1 -gpgpu_memory_partition_indexing 0 # 128 KB Inst. -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 -gpgpu_inst_fetch_throughput 4 # 128 KB Tex # Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod -gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 # 64 KB Const -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 -gpgpu_perfect_inst_const_cache 1 # interconnection #-network_mode 1 #-inter_config_file config_turing_islip.icnt # use built-in local xbar -network_mode 2 -icnt_in_buffer_limit 512 -icnt_out_buffer_limit 512 -icnt_subnets 2 -icnt_arbiter_algo 1 -icnt_flit_size 40 # memory partition latency config -gpgpu_l2_rop_latency 160 -dram_latency 100 # dram model config -gpgpu_dram_scheduler 1 -gpgpu_frfcfs_dram_sched_queue_size 64 -gpgpu_dram_return_queue_size 192 # Turing has GDDR6 # http://monitorinsider.com/GDDR6.html -gpgpu_n_mem_per_ctrlr 1 -gpgpu_dram_buswidth 2 -gpgpu_dram_burst_length 16 -dram_data_command_freq_ratio 4 -gpgpu_mem_address_mask 1 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # Use the same GDDR5 timing, scaled to 3500MHZ -gpgpu_dram_timing_opt "nbk=16:CCD=4:RRD=10:RCD=20:RAS=50:RP=20:RC=62: CL=20:WL=8:CDLR=9:WR=20:nbkgrp=4:CCDL=4:RTPL=4" # select lower bits for bnkgrp to increase bnkgrp parallelism -dram_bnk_indexing_policy 0 -dram_bnkgrp_indexing_policy 1 #-dram_seperate_write_queue_enable 1 #-dram_write_queue_size 64:56:32 # stat collection -gpgpu_memlatency_stat 14 -gpgpu_runtime_stat 500 -enable_ptx_file_line_stats 1 -visualizer_enabled 0 # power model configs, disable it untill we create a real energy model for Volta -power_simulation_enabled 0 # tracing functionality #-trace_enabled 1 #-trace_components WARP_SCHEDULER,SCOREBOARD #-trace_sampling_core 0