/* * mem_fetch.cc * * Copyright (c) 2009 by Tor M. Aamodt and * University of British Columbia * Vancouver, BC V6T 1Z4 * All Rights Reserved. * * THIS IS A LEGAL DOCUMENT BY DOWNLOADING GPGPU-SIM, YOU ARE AGREEING TO THESE * TERMS AND CONDITIONS. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNERS OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * NOTE: The files libcuda/cuda_runtime_api.c and src/cuda-sim/cuda-math.h * are derived from the CUDA Toolset available from http://www.nvidia.com/cuda * (property of NVIDIA). The files benchmarks/BlackScholes/ and * benchmarks/template/ are derived from the CUDA SDK available from * http://www.nvidia.com/cuda (also property of NVIDIA). The files from * src/intersim/ are derived from Booksim (a simulator provided with the * textbook "Principles and Practices of Interconnection Networks" available * from http://cva.stanford.edu/books/ppin/). As such, those files are bound by * the corresponding legal terms and conditions set forth separately (original * copyright notices are left in files from these sources and where we have * modified a file our copyright notice appears before the original copyright * notice). * * Using this version of GPGPU-Sim requires a complete installation of CUDA * which is distributed seperately by NVIDIA under separate terms and * conditions. To use this version of GPGPU-Sim with OpenCL requires a * recent version of NVIDIA's drivers which support OpenCL. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * 3. Neither the name of the University of British Columbia nor the names of * its contributors may be used to endorse or promote products derived from * this software without specific prior written permission. * * 4. This version of GPGPU-SIM is distributed freely for non-commercial use only. * * 5. No nonprofit user may place any restrictions on the use of this software, * including as modified by the user, by any other authorized user. * * 6. GPGPU-SIM was developed primarily by Tor M. Aamodt, Wilson W. L. Fung, * Ali Bakhoda, George L. Yuan, at the University of British Columbia, * Vancouver, BC V6T 1Z4 */ #include "mem_fetch.h" #include "mem_latency_stat.h" #include "shader.h" #include "visualizer.h" #include "gpu-sim.h" unsigned mem_fetch::sm_next_mf_request_uid=1; mem_fetch::mem_fetch( new_addr_type addr, unsigned data_size, unsigned ctrl_size, unsigned sid, unsigned tpc, unsigned wid, warp_inst_t *inst, bool write, partial_write_mask_t partial_write_mask, enum mem_access_type mem_acc, enum mf_type type, const memory_config *config ) : m_inst() { m_request_uid = sm_next_mf_request_uid++; m_addr = addr; m_data_size = data_size; m_ctrl_size = ctrl_size; m_sid = sid; m_wid = wid; m_tpc = tpc; if( inst ) m_inst = *inst; m_write = write; config->m_address_mapping.addrdec_tlx(addr,&m_raw_addr); m_partition_addr = config->m_address_mapping.partition_address(addr); m_mem_acc = mem_acc; m_type = type; m_timestamp = gpu_sim_cycle + gpu_tot_sim_cycle; m_timestamp2 = 0; m_status = MEM_FETCH_INITIALIZED; m_status_change = gpu_sim_cycle + gpu_tot_sim_cycle; } mem_fetch::~mem_fetch() { m_status = MEM_FETCH_DELETED; } static const char* Status_str[] = { "INITIALIZED", "IN_ICNT_TO_MEM", "IN_PARTITION_ROP_DELAY", "IN_PARTITION_ICNT_TO_L2_QUEUE", "IN_PARTITION_L2_TO_DRAM_QUEUE", "IN_PARTITION_MC_INTERFACE_QUEUE", "IN_PARTITION_MC_INPUT_QUEUE", "IN_PARTITION_MC_BANK_ARB_QUEUE", "IN_PARTITION_DRAM", "IN_PARTITION_MC_RETURNQ", "IN_PARTITION_DRAM_TO_L2_QUEUE", "IN_PARTITION_L2_FILL_QUEUE", "IN_PARTITION_L2_TO_ICNT_QUEUE", "IN_ICNT_TO_SHADER", "IN_CLUSTER_TO_SHADER_QUEUE", "IN_SHADER_LDST_RESPONSE_FIFO", "IN_SHADER_FETCHED", "MEM_FETCH_DELETED" }; void mem_fetch::print( FILE *fp, bool print_inst ) const { if( this == NULL ) { fprintf(fp," \n"); return; } fprintf(fp," mf: uid=%6u, addr=0x%08llx, sid=%2u, wid=%2u, %s, partition=%u, ", m_request_uid, m_addr, m_sid, m_wid, (m_write?"write":"read "), m_raw_addr.chip); if( (unsigned)m_status < NUM_MEM_REQ_STAT ) fprintf(fp," status = %s (%llu), ", Status_str[m_status], m_status_change ); else fprintf(fp," status = %u??? (%llu), ", m_status, m_status_change ); if( !m_inst.empty() && print_inst ) m_inst.print(fp); else fprintf(fp,"\n"); } void mem_fetch::set_status( enum mem_fetch_status status, unsigned long long cycle ) { m_status = status; m_status_change = cycle; } bool mem_fetch::isatomic() const { if( m_inst.empty() ) return false; return m_inst.isatomic(); } void mem_fetch::do_atomic() { m_inst.do_atomic(); } bool mem_fetch::istexture() const { if( m_inst.empty() ) return false; return m_inst.space.get_type() == tex_space; } bool mem_fetch::isconst() const { if( m_inst.empty() ) return false; return (m_inst.space.get_type() == const_space) || (m_inst.space.get_type() == param_space_kernel); }