/* 
 * mem_fetch.h
 *
 * Copyright (c) 2009 by Tor M. Aamodt, Wilson W. L. Fung, Ali Bakhoda, 
 * George L. Yuan and the 
 * University of British Columbia
 * Vancouver, BC  V6T 1Z4
 * All Rights Reserved.
 * 
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 * 
 * NOTE: The files libcuda/cuda_runtime_api.c and src/cuda-sim/cuda-math.h
 * are derived from the CUDA Toolset available from http://www.nvidia.com/cuda
 * (property of NVIDIA).  The files benchmarks/BlackScholes/ and 
 * benchmarks/template/ are derived from the CUDA SDK available from 
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 * src/intersim/ are derived from Booksim (a simulator provided with the 
 * textbook "Principles and Practices of Interconnection Networks" available 
 * from http://cva.stanford.edu/books/ppin/). As such, those files are bound by 
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 * notice).  
 * 
 * Using this version of GPGPU-Sim requires a complete installation of CUDA 
 * which is distributed seperately by NVIDIA under separate terms and 
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 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
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 * 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
 * 
 * 2. Redistributions in binary form must reproduce the above copyright notice,
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 * 4. This version of GPGPU-SIM is distributed freely for non-commercial use only.  
 *  
 * 5. No nonprofit user may place any restrictions on the use of this software,
 * including as modified by the user, by any other authorized user.
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 * 6. GPGPU-SIM was developed primarily by Tor M. Aamodt, Wilson W. L. Fung, 
 * Ali Bakhoda, George L. Yuan, at the University of British Columbia, 
 * Vancouver, BC V6T 1Z4
 */

#ifndef MEM_FETCH_H
#define MEM_FETCH_H

#include "shader.h"
#include "addrdec.h"

enum mf_type {
   RD_REQ = 0,
   WT_REQ,
   REPLY_DATA, // send to shader
   L2_WTBK_DATA,
   DUMMY_READ, //used in write mask    
   N_MF_TYPE
};

typedef struct {
   unsigned request_uid;
   unsigned long long int addr;
   int nbytes_L1;
   int txbytes_L1;
   int rxbytes_L1;
   int nbytes_L2;
   int txbytes_L2;
   int rxbytes_L2;
   int sid; //shader core id
   int wid; //warp id
   int cache_hits_waiting;
   mshr_entry* mshr;
   address_type pc;
   unsigned char write;
   enum mem_access_type mem_acc;
   unsigned int timestamp; //set to gpu_sim_cycle at struct creation
   unsigned int timestamp2; //set to gpu_sim_cycle when pushed onto icnt to shader; only used for reads
   unsigned int icnt_receive_time; //set to gpu_sim_cycle + interconnect_latency when fixed icnt latency mode is enabled
   unsigned char bank;
   unsigned char chip;
   addrdec_t tlx;
   enum mf_type type;
   partial_write_mask_t write_mask;
   int source_node; //memory node id when sending from mem to shader
                    //same as sid when sending from shader 2 mem 
} mem_fetch_t;

#endif