/* * mem_latency_stat.h * * Copyright (c) 2009 by Tor M. Aamodt, Wilson W. L. Fung, Ali Bakhoda, * George L. Yuan and the * University of British Columbia * Vancouver, BC V6T 1Z4 * All Rights Reserved. * * THIS IS A LEGAL DOCUMENT BY DOWNLOADING GPGPU-SIM, YOU ARE AGREEING TO THESE * TERMS AND CONDITIONS. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. 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Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * 3. Neither the name of the University of British Columbia nor the names of * its contributors may be used to endorse or promote products derived from * this software without specific prior written permission. * * 4. This version of GPGPU-SIM is distributed freely for non-commercial use only. * * 5. No nonprofit user may place any restrictions on the use of this software, * including as modified by the user, by any other authorized user. * * 6. GPGPU-SIM was developed primarily by Tor M. Aamodt, Wilson W. L. Fung, * Ali Bakhoda, George L. Yuan, at the University of British Columbia, * Vancouver, BC V6T 1Z4 */ #ifndef MEM_LATENCY_STAT_H #define MEM_LATENCY_STAT_H #include #include class memory_stats_t { public: memory_stats_t( unsigned n_shader, const struct shader_core_config *shader_config, const struct memory_config *mem_config ); unsigned memlatstat_done( class mem_fetch *mf ); void memlatstat_read_done( class mem_fetch *mf ); void memlatstat_dram_access( class mem_fetch *mf ); void memlatstat_icnt2mem_pop( class mem_fetch *mf); void memlatstat_lat_pw(); void memlatstat_print(unsigned n_mem, unsigned gpu_mem_n_bk); void print( FILE *fp ); void visualizer_print( gzFile visualizer_file ); unsigned m_n_shader; const struct shader_core_config *m_shader_config; const struct memory_config *m_memory_config; unsigned max_mrq_latency; unsigned max_dq_latency; unsigned max_mf_latency; unsigned max_icnt2mem_latency; unsigned max_icnt2sh_latency; unsigned mrq_lat_table[32]; unsigned dq_lat_table[32]; unsigned mf_lat_table[32]; unsigned icnt2mem_lat_table[24]; unsigned icnt2sh_lat_table[24]; unsigned mf_lat_pw_table[32]; //table storing values of mf latency Per Window unsigned mf_num_lat_pw; unsigned max_warps; unsigned mf_tot_lat_pw; //total latency summed up per window. divide by mf_num_lat_pw to obtain average latency Per Window unsigned long long int mf_total_lat; unsigned long long int ** mf_total_lat_table; //mf latency sums[dram chip id][bank id] unsigned ** mf_max_lat_table; //mf latency sums[dram chip id][bank id] unsigned num_mfs; unsigned int ***bankwrites; //bankwrites[shader id][dram chip id][bank id] unsigned int ***bankreads; //bankreads[shader id][dram chip id][bank id] unsigned int **totalbankwrites; //bankwrites[dram chip id][bank id] unsigned int **totalbankreads; //bankreads[dram chip id][bank id] unsigned int **totalbankaccesses; //bankaccesses[dram chip id][bank id] unsigned int *num_MCBs_accessed; //tracks how many memory controllers are accessed whenever any thread in a warp misses in cache unsigned int *position_of_mrq_chosen; //position of mrq in m_queue chosen unsigned ***mem_access_type_stats; // dram access type classification // stats unsigned L2_write_miss; unsigned L2_write_hit; unsigned L2_read_hit; unsigned L2_read_miss; unsigned int *L2_cbtoL2length; unsigned int *L2_cbtoL2writelength; unsigned int *L2_L2tocblength; unsigned int *L2_dramtoL2length; unsigned int *L2_dramtoL2writelength; unsigned int *L2_L2todramlength; unsigned int **concurrent_row_access; //concurrent_row_access[dram chip id][bank id] unsigned int **num_activates; //num_activates[dram chip id][bank id] unsigned int **row_access; //row_access[dram chip id][bank id] unsigned int **max_conc_access2samerow; //max_conc_access2samerow[dram chip id][bank id] unsigned int **max_servicetime2samerow; //max_servicetime2samerow[dram chip id][bank id] }; #endif /*MEM_LATENCY_STAT_H*/