adding new stats and change the PascalP100-HBM config

8 files changed, 63 insertions, 24 deletions

diff --git a/configs/Pascal-P100-HBM/config_fermi_islip.icnt b/configs/Pascal-P100-HBM/config_fermi_islip.icnt
index a788090..0a73c81 100644
--- a/configs/Pascal-P100-HBM/config_fermi_islip.icnt
+++ b/configs/Pascal-P100-HBM/config_fermi_islip.icnt
@@ -1,13 +1,13 @@
 //21*1 fly with 32 flits per packet under gpgpusim injection mode
 use_map = 0;
-flit_size = 32; 
+flit_size = 40; 
 
 // currently we do not use this, see subnets below
 network_count = 2;
 
 // Topology
 topology = fly;
-k = 62;
+k = 60;
 n = 1;
 
 // Routing
@@ -17,7 +17,10 @@ routing_function = dest_tag;
 // Flow control
 
 num_vcs     = 1;
-vc_buf_size = 8;
+vc_buf_size = 64;
+input_buffer_size = 64;
+ejection_buffer_size = 64;
+boundary_buffer_size = 64;
 
 wait_for_tail_credit = 0;
 
diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config
index 5b038de..1029194 100644
--- a/configs/Pascal-P100-HBM/gpgpusim.config
+++ b/configs/Pascal-P100-HBM/gpgpusim.config
@@ -54,13 +54,17 @@
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
 # Pascal GP100 has 64KB Shared memory
--gpgpu_cache:dl1  N:64:128:6,L:L:m:N:H,S:128:8,8
+-gpgpu_cache:dl1  S:64:128:6,L:L:m:N:H,A:128:8,32:0,32
 -gpgpu_shmem_size 65536
--gmem_skip_L1D 0
+-gmem_skip_L1D 1
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
 
-# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives  4MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:128:4,4:0,32
+# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives  4MB L2 cache
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:256:4,32:0,32
 -gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+#-gpgpu_flush_l2_cache 1
 
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
@@ -89,8 +93,7 @@
 -gpgpu_shmem_num_banks 32
 -gpgpu_shmem_limited_broadcast 0
 -gpgpu_shmem_warp_parts 1
-# Use Fermi Coalscer arhitetecture for now! Need to be canged to pascal Coalscer
--gpgpu_coalesce_arch 20
+-gpgpu_coalesce_arch 60
 
 ## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
 -gpgpu_max_insn_issue_per_warp 2
@@ -123,10 +126,6 @@
 -gpgpu_mem_address_mask 1
 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
 
-# GDDR5 timing
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-#                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
-
 # HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
 # Timing for 1 GHZ
 # tRRDl and tWTR are missing, need to be added
@@ -140,8 +139,12 @@
 # HBM has dual bus interface, in which it can issue two col and row commands at a time
 -dual_bus_interface 1
 # select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
 -dram_bnkgrp_indexing_policy 1
 
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
 # Pascal has two schedulers per core
 -gpgpu_num_sched_per_core 2
 # Two Level Scheduler with active and pending pools
@@ -158,7 +161,7 @@
 -visualizer_enabled 0
 
 # power model configs, disable it untill we create a real energy model for Pascal 100
--power_simulation_enabled 1
+-power_simulation_enabled 0
 -gpuwattch_xml_file gpuwattch_gtx480.xml
 
 # tracing functionality
diff --git a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt
index 58e596d..94b2378 100644
--- a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt
+++ b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt
@@ -18,6 +18,9 @@ routing_function = dest_tag;
 
 num_vcs     = 1;
 vc_buf_size = 32;
+input_buffer_size = 32;
+ejection_buffer_size = 32;
+boundary_buffer_size = 32;
 
 wait_for_tail_credit = 0;
 
diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc
index de37f64..a57508c 100644
--- a/src/gpgpu-sim/dram.cc
+++ b/src/gpgpu-sim/dram.cc
@@ -52,6 +52,10 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m
    //rowblp
    access_num=0;
    hits_num=0;
+   read_num=0;
+   write_num=0;
+   hits_read_num=0;
+   hits_write_num=0;
    banks_1time=0;
    banks_acess_total=0;
    banks_acess_total_after=0;
@@ -718,6 +722,8 @@ void dram_t::print( FILE* simFile) const
    fprintf(simFile, "\n------------------------------------------------------------------------\n");
 
    printf("\nRow_Buffer_Locality = %.6f", (float)hits_num / access_num);
+   printf("\nRow_Buffer_Locality_read = %.6f", (float)hits_read_num / read_num);
+   printf("\nRow_Buffer_Locality_write = %.6f", (float)hits_write_num / write_num);
    printf("\nBank_Level_Parallism = %.6f", (float)banks_1time / banks_acess_total);
    printf("\nBank_Level_Parallism_Col = %.6f", (float)banks_time_rw / banks_access_rw_total);
    printf("\nBank_Level_Parallism_Ready = %.6f", (float)banks_time_ready /banks_access_ready_total);
@@ -735,7 +741,7 @@ void dram_t::print( FILE* simFile) const
    printf("RCDWRc_limit = %d \n", RCDWRc_limit);
    printf("WTRc_limit = %d \n", WTRc_limit);
    printf("RTWc_limit = %d \n", RTWc_limit);
-   printf("CCDLc_limit %d \n", CCDLc_limit);
+   printf("CCDLc_limit = %d \n", CCDLc_limit);
    printf("rwq = %d \n", rwq_limit);
    printf("CCDLc_limit_alone = %d \n", CCDLc_limit_alone);
    printf("WTRc_limit_alone = %d \n", WTRc_limit_alone);
@@ -751,15 +757,14 @@ void dram_t::print( FILE* simFile) const
    printf("n_pre = %d \n", n_pre);
    printf("n_ref = %d \n", n_ref);
    printf("n_req = %d \n", n_req );
-   printf("n_req4 = %d \n", n_req*4 );
    printf("total_req = %d \n\n", n_rd+n_wr+n_rd_L2_A+n_wr_WB);
 
    printf("issued_total_row = %lu \n", issued_total_row);
    printf("issued_total_col = %lu \n", issued_total_col);
    printf("Row_Bus_Util =  %.6f \n", (float)issued_total_row / n_cmd);
    printf("CoL_Bus_Util = %.6f \n", (float)issued_total_col / n_cmd);
-   printf("Either_Row_CoL_Bus_Util %.6f \n",  (float)issued_total / n_cmd);
-   printf("Issued_on_Two_Bus_Simul_Util %.6f \n",  (float)issued_two /n_cmd);
+   printf("Either_Row_CoL_Bus_Util = %.6f \n",  (float)issued_total / n_cmd);
+   printf("Issued_on_Two_Bus_Simul_Util = %.6f \n",  (float)issued_two /n_cmd);
    printf("issued_two_Eff = %.6f \n",  (float)issued_two /issued_total);
    printf("queue_avg = %.6f \n\n", (float)ave_mrqs/n_cmd );
 
diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h
index 29731a7..0d4c0e7 100644
--- a/src/gpgpu-sim/dram.h
+++ b/src/gpgpu-sim/dram.h
@@ -198,7 +198,11 @@ private:
 
    //row locality, BLP and other statistics
    unsigned long  access_num;
+   unsigned long  read_num;
+   unsigned long  write_num;
    unsigned long long hits_num;
+   unsigned long long hits_read_num;
+   unsigned long long hits_write_num;
    unsigned long long banks_1time;
    unsigned long long banks_acess_total;
    unsigned long long banks_acess_total_after;
diff --git a/src/gpgpu-sim/dram_sched.cc b/src/gpgpu-sim/dram_sched.cc
index ac4c827..f754d36 100644
--- a/src/gpgpu-sim/dram_sched.cc
+++ b/src/gpgpu-sim/dram_sched.cc
@@ -142,14 +142,25 @@ dram_req_t *frfcfs_scheduler::schedule( unsigned bank, unsigned curr_row )
          rowhit = true;
       }
    }
-   //rowblp
-  m_dram->access_num++;
-  if(rowhit)
-   m_dram->hits_num++;
-
    std::list<dram_req_t*>::iterator next = m_current_last_row[bank]->back();
    dram_req_t *req = (*next);
 
+   //rowblp stats
+    m_dram->access_num++;
+    bool is_write = req->data->is_write();
+    if(is_write)
+  	  m_dram->write_num++;
+    else
+  	  m_dram->read_num++;
+
+    if(rowhit) {
+     m_dram->hits_num++;
+     if(is_write)
+    	  m_dram->hits_write_num++;
+      else
+    	  m_dram->hits_read_num++;
+    }
+
    m_stats->concurrent_row_access[m_dram->id][bank]++;
    m_stats->row_access[m_dram->id][bank]++;
    m_current_last_row[bank]->pop_back();
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 0e06c5c..11ac5df 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -207,6 +207,9 @@ void memory_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-Write_Queue_Size", OPT_CSTR, &write_queue_size_opt,
                                   "Write_Queue_Size",
                                   "32:28:16");
+    option_parser_register(opp, "-Elimnate_rw_turnaround", OPT_BOOL, &elimnate_rw_turnaround,
+                               "elimnate_rw_turnaround i.e set tWTR and tRTW = 0",
+                               "0");
     option_parser_register(opp, "-icnt_flit_size", OPT_UINT32, &icnt_flit_size,
                                "icnt_flit_size",
                                "32");
@@ -435,7 +438,6 @@ void gpgpu_sim_config::reg_options(option_parser_t opp)
    option_parser_register(opp, "-gpgpu_flush_l2_cache", OPT_BOOL, &gpgpu_flush_l2_cache,
                    "Flush L2 cache at the end of each kernel call",
                    "0");
-
    option_parser_register(opp, "-gpgpu_deadlock_detect", OPT_BOOL, &gpu_deadlock_detect, 
                 "Stop the simulation at deadlock (1=on (default), 0=off)", 
                 "1");
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index 043fcee..c04648c 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -198,8 +198,14 @@ struct memory_config {
       bk_tag_length = i-1;
       assert(nbkgrp>0 && "Number of bank groups cannot be zero");
       tRCDWR = tRCD-(WL+1);
+      if(elimnate_rw_turnaround)
+      {
+    	  tRTW = 0;
+    	  tWTR = 0;
+      } else {
       tRTW = (CL+(BL/data_command_freq_ratio)+2-WL);
       tWTR = (WL+(BL/data_command_freq_ratio)+tCDLR);
+      }
       tWTP = (WL+(BL/data_command_freq_ratio)+tWR);
       dram_atom_size = BL * busW * gpu_n_mem_per_ctrlr; // burst length x bus width x # chips per partition 
 
@@ -266,6 +272,8 @@ struct memory_config {
 
    unsigned nbk;
 
+   bool elimnate_rw_turnaround;
+
    unsigned data_command_freq_ratio; // frequency ratio between DRAM data bus and command bus (2 for GDDR3, 4 for GDDR5)
    unsigned dram_atom_size; // number of bytes transferred per read or write command