Fixed the DRAM timing model to add the write-read turn and write-precharge delay. Still need to update/validate the Quadro config for this.

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9921]

4 files changed, 15 insertions, 5 deletions

diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc
index fb95673..b09033f 100644
--- a/src/gpgpu-sim/dram.cc
+++ b/src/gpgpu-sim/dram.cc
@@ -294,6 +294,8 @@ void dram_t::cycle()
 
             bk[j]->mrq->txbytes += m_config->BL * m_config->busW * m_config->gpu_n_mem_per_ctrlr; /*16 bytes*/
             CCDc = m_config->tCCD;
+            WTRc = m_config->tWTR; 
+            bk[j]->WTPc = m_config->tWTP; 
             issued = true;
             n_wr++;
             bwutil+=2;
@@ -339,7 +341,7 @@ void dram_t::cycle()
             if ( (!issued) && 
                  (bk[j]->curr_row != bk[j]->mrq->row) &&
                  (bk[j]->state == BANK_ACTIVE) && 
-                 (!bk[j]->RASc) ) {
+                 (!bk[j]->RASc && !bk[j]->WTPc) ) {
             // make the bank idle again
             bk[j]->state = BANK_IDLE;
             bk[j]->RPc = m_config->tRP;
@@ -383,6 +385,7 @@ void dram_t::cycle()
       DEC2ZERO(bk[j]->RCc);
       DEC2ZERO(bk[j]->RPc);
       DEC2ZERO(bk[j]->RCDWRc);
+      DEC2ZERO(bk[j]->WTPc); 
    }
 
 #ifdef DRAM_VISUALIZE
diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h
index 4cbcbb3..6a28058 100644
--- a/src/gpgpu-sim/dram.h
+++ b/src/gpgpu-sim/dram.h
@@ -65,6 +65,7 @@ struct bank_t
    unsigned int RASc;
    unsigned int RPc;
    unsigned int RCc;
+   unsigned int WTPc; // write to precharge 
 
    unsigned char rw;    //is the bank reading or writing?
    unsigned char state; //is the bank active or idle?
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 243574e..d29247c 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -123,8 +123,8 @@ void memory_config::reg_options(class OptionParser * opp)
                  "Burst length of each DRAM request (default = 4 DDR cycle)",
                  "4");
     option_parser_register(opp, "-gpgpu_dram_timing_opt", OPT_CSTR, &gpgpu_dram_timing_opt, 
-                "DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tWTR}",
-                "4:2:8:12:21:13:34:9:4:5");
+                "DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR}",
+                "4:2:8:12:21:13:34:9:4:5:13");
 
     m_address_mapping.addrdec_setoption(opp);
 }
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index 2dcc1fe..396b884 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -72,9 +72,12 @@ struct memory_config {
    void init()
    {
       assert(gpgpu_dram_timing_opt);
-      sscanf(gpgpu_dram_timing_opt,"%d:%d:%d:%d:%d:%d:%d:%d:%d:%d",&nbk,&tCCD,&tRRD,&tRCD,&tRAS,&tRP,&tRC,&CL,&WL,&tWTR);
+      sscanf(gpgpu_dram_timing_opt,"%d:%d:%d:%d:%d:%d:%d:%d:%d:%d:%d",
+             &nbk,&tCCD,&tRRD,&tRCD,&tRAS,&tRP,&tRC,&CL,&WL,&tCDLR,&tWR);
       tRCDWR = tRCD-(WL+1);
       tRTW = (CL+(BL/2)+2-WL);
+      tWTR = (WL+(BL/2)+tCDLR); 
+      tWTP = (WL+(BL/2)+tWR);
       m_address_mapping.init(m_n_mem);
       m_L2_config.init();
       m_valid = true;
@@ -102,12 +105,15 @@ struct memory_config {
    unsigned tRAS;   //time needed to activate row
    unsigned tRP;    //row precharge ie. deactivate row
    unsigned tRC;    //row cycle time ie. precharge current, then activate different row
+   unsigned tCDLR;  //Last data-in to Read command (switching from write to read)
+   unsigned tWR;    //Last data-in to Row precharge 
 
    unsigned CL;     //CAS latency
    unsigned WL;     //WRITE latency
    unsigned BL;     //Burst Length in bytes (we're using 4? could be 8)
    unsigned tRTW;   //time to switch from read to write
-   unsigned tWTR;   //time to switch from write to read 5? look in datasheet
+   unsigned tWTR;   //time to switch from write to read 
+   unsigned tWTP;   //time to switch from write to precharge in the same bank
    unsigned busW;
 
    unsigned nbk;