removing some comments and refectoring the code

6 files changed, 32 insertions, 66 deletions

diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index 063aa8d..758ec00 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -471,8 +471,7 @@ void warp_inst_t::generate_mem_accesses()
     }
 
     if ( space.get_type() == global_space ) {
-    	//TO DO: check here
-       // m_config->gpgpu_ctx->stats->ptx_file_line_stats_add_uncoalesced_gmem( pc, m_accessq.size() - starting_queue_size );
+        m_config->gpgpu_ctx->stats->ptx_file_line_stats_add_uncoalesced_gmem( pc, m_accessq.size() - starting_queue_size );
     }
     m_mem_accesses_created=true;
 }
@@ -707,9 +706,7 @@ void warp_inst_t::completed( unsigned long long cycle ) const
 {
    unsigned long long latency = cycle - issue_cycle; 
    assert(latency <= cycle); // underflow detection 
-   //check the trace mode here
-   //TO DO
-   //m_config->gpgpu_ctx->stats->ptx_file_line_stats_add_latency(pc, latency * active_count());
+   m_config->gpgpu_ctx->stats->ptx_file_line_stats_add_latency(pc, latency * active_count());
 }
 
 
diff --git a/src/cuda-sim/ptx-stats.cc b/src/cuda-sim/ptx-stats.cc
index 22517df..2af65e5 100644
--- a/src/cuda-sim/ptx-stats.cc
+++ b/src/cuda-sim/ptx-stats.cc
@@ -154,8 +154,9 @@ void ptx_file_line_stats_add_exec_count(const ptx_instruction *pInsn)
 void ptx_stats::ptx_file_line_stats_add_latency(unsigned pc, unsigned latency)
 {
     const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc);
-    
-    ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), pInsn->source_line())].latency += latency;
+
+    if(pInsn != NULL)
+    	ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), pInsn->source_line())].latency += latency;
 }
 
 // attribute dram traffic to this ptx instruction (specified by the pc)
@@ -164,7 +165,8 @@ void ptx_stats::ptx_file_line_stats_add_dram_traffic(unsigned pc, unsigned dram_
 {
     const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc);
     
-    ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), pInsn->source_line())].dram_traffic += dram_traffic;
+    if(pInsn != NULL)
+    	ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), pInsn->source_line())].dram_traffic += dram_traffic;
 }
 
 // attribute the number of shared memory access cycles to a ptx instruction
@@ -173,9 +175,11 @@ void ptx_stats::ptx_file_line_stats_add_smem_bank_conflict(unsigned pc, unsigned
 {
     const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc);
     
-    ptx_file_line_stats& line_stats = ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), pInsn->source_line())];
-    line_stats.smem_n_way_bank_conflict_total += n_way_bkconflict;
-    line_stats.smem_warp_count += 1;
+    if(pInsn != NULL) {
+    	ptx_file_line_stats& line_stats = ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), pInsn->source_line())];
+    	line_stats.smem_n_way_bank_conflict_total += n_way_bkconflict;
+    	line_stats.smem_warp_count += 1;
+    }
 }
 
 // attribute a non-coalesced mem access to a ptx instruction 
@@ -184,9 +188,11 @@ void ptx_stats::ptx_file_line_stats_add_uncoalesced_gmem(unsigned pc, unsigned n
 {
     const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc);
     
-    ptx_file_line_stats& line_stats = ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), pInsn->source_line())];
-    line_stats.gmem_n_access_total += n_access;
-    line_stats.gmem_warp_count += 1;
+    if(pInsn != NULL) {
+		ptx_file_line_stats& line_stats = ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), pInsn->source_line())];
+		line_stats.gmem_n_access_total += n_access;
+		line_stats.gmem_warp_count += 1;
+    }
 }
 
 // a class that tracks the inflight memory instructions of a shader core 
diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc
index 1980a3b..2141e10 100644
--- a/src/gpgpu-sim/mem_latency_stat.cc
+++ b/src/gpgpu-sim/mem_latency_stat.cc
@@ -195,9 +195,9 @@ void memory_stats_t::memlatstat_dram_access(mem_fetch *mf)
       }
       mem_access_type_stats[mf->get_access_type()][dram_id][bank]++;
    }
-	 //TO DO: check here
-   //if (mf->get_pc() != (unsigned)-1)
-     // m_gpu->gpgpu_ctx->stats->ptx_file_line_stats_add_dram_traffic(mf->get_pc(), mf->get_data_size());
+
+   if (mf->get_pc() != (unsigned)-1)
+      m_gpu->gpgpu_ctx->stats->ptx_file_line_stats_add_dram_traffic(mf->get_pc(), mf->get_data_size());
 }
 
 void memory_stats_t::memlatstat_icnt2mem_pop(mem_fetch *mf)
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 8dddc36..cc85f3f 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -3290,10 +3290,6 @@ void barrier_set_t::deallocate_barrier( unsigned cta_id )
    warp_set_t at_barrier = warps & m_warp_at_barrier;
    assert( at_barrier.any() == false ); // no warps stuck at barrier
    warp_set_t active = warps & m_warp_active;
-   std::cout<<active<<std::endl;
-   std::cout<<warps<<std::endl;
-   std::cout<<m_warp_active<<std::endl;
-
    assert( active.any() == false ); // no warps in CTA still running
    m_warp_active &= ~warps;
    m_warp_at_barrier &= ~warps;
diff --git a/src/trace-driven/gpgpusim_trace_driven_main.cc b/src/trace-driven/gpgpusim_trace_driven_main.cc
index fea56c1..76c2cda 100644
--- a/src/trace-driven/gpgpusim_trace_driven_main.cc
+++ b/src/trace-driven/gpgpusim_trace_driven_main.cc
@@ -16,18 +16,10 @@
 #include "../cuda-sim/ptx_ir.h"
 #include "../cuda-sim/ptx_parser.h"
 #include "../gpgpu-sim/gpu-sim.h"
-//#include "../gpgpu-sim/icnt_wrapper.h"
-//#include "../gpgpu-sim/icnt_wrapper.h"
 #include "../../libcuda/gpgpu_context.h"
 #include "trace_driven.h"
 #include "trace_opcode.h"
 #include "../gpgpusim_entrypoint.h"
-//#include "gpgpu_context.h"
-
-//#include "../stream_manager.h"
-
-
-void arguments_check();
 
 
 int main ( int argc, const char **argv )
@@ -243,8 +235,6 @@ bool trace_kernel_info_t::get_next_threadblock_traces(std::vector<std::vector<tr
 	for(unsigned i=0; i<threadblock_traces.size(); ++i) {
 		threadblock_traces[i]->clear();
 	}
-	//unsigned warps_per_tb = ceil(float(threads_per_cta()/32));
-	//threadblock_traces.resize(warps_per_tb);
 
 	unsigned block_id_x=0, block_id_y=0, block_id_z=0;
 	unsigned warp_id=0;
@@ -273,11 +263,9 @@ bool trace_kernel_info_t::get_next_threadblock_traces(std::vector<std::vector<tr
 				}
 				else
 					assert(0 && "Parsing error: thread block start before the previous one finish");
-				std::cout<<line<<std::endl;
 			}
 			else if (string1 == "#END_TB") {
 				assert(start_of_tb_stream_found);
-				std::cout<<line<< std::endl;
 				break; //end of TB stream
 			}
 			else if(string1 == "thread" && string2 == "block") {
@@ -289,18 +277,15 @@ bool trace_kernel_info_t::get_next_threadblock_traces(std::vector<std::vector<tr
 				//the start of new warp stream
 				assert(start_of_tb_stream_found);
 				sscanf(line.c_str(), "warp = %d", &warp_id);
-				//std::cout << line << std::endl;
 			}
 			else if (string1 == "insts") {
 				assert(start_of_tb_stream_found);
 				sscanf(line.c_str(), "insts = %d", &insts_num);
 				threadblock_traces[warp_id]->reserve(insts_num);
-				//std::cout << line << std::endl;
 			}
 			else {
 				assert(start_of_tb_stream_found);
 				trace_warp_inst_t inst(m_gpgpu_sim->getShaderCoreConfig(), m_gpgpu_context);
-				//std::cout<<line << std::endl;
 				inst.parse_from_string(line);
 				threadblock_traces[warp_id]->push_back(inst);
 			}
@@ -329,16 +314,15 @@ bool trace_warp_inst_t::parse_from_string(std::string trace){
 	unsigned mem_width=0;
 	unsigned long long mem_addresses[warp_size()];
 
+	//Start Parsing
 	ss>>std::dec>>threadblock_x>>threadblock_y>>threadblock_z>>warpid_tb>>sm_id>>warpid_sm;
 
-	ss>>std::hex>>m_pc>>mask;
-	//std::cout<<"m_pc= "<<m_pc<<std::endl;
-	//std::cout<<"mask= "<<mask<<std::endl;
+	ss>>std::hex>>m_pc;
+	ss>>std::hex>>mask;
 
 	std::bitset<MAX_WARP_SIZE> mask_bits(mask);
 
-	ss>>reg_dsts_num;
-
+	ss>>std::dec>>reg_dsts_num;
 	for(unsigned i=0; i<reg_dsts_num; ++i) {
 		ss>>std::dec>>temp;
 		sscanf(temp.c_str(), "R%d", &reg_dest[i]);
@@ -347,7 +331,6 @@ bool trace_warp_inst_t::parse_from_string(std::string trace){
 	ss>>opcode;
 
 	ss>>reg_srcs_num;
-
 	for(unsigned i=0; i<reg_srcs_num; ++i) {
 		ss>>temp;
 		sscanf(temp.c_str(), "R%d", &reg_srcs[i]);
@@ -365,7 +348,7 @@ bool trace_warp_inst_t::parse_from_string(std::string trace){
 				mem_addresses[s]=0;
 		}
 	}
-
+	//Finish Parsing
 	//After parsing, fill the inst_t and warp_inst_t params
 
 	//fill active mask
@@ -378,7 +361,6 @@ bool trace_warp_inst_t::parse_from_string(std::string trace){
 	//fill and initialize common params
 	m_decoded = true;
 	pc = (address_type)m_pc;   //we will lose the high 32 bits from casting long to unsigned, it should be okay!
-	//std::cout<<"pc= "<<pc<<std::endl;
 
 	isize = 16;   //TO DO, change this
 	for(unsigned i=0; i<MAX_OUTPUT_VALUES; i++) {
@@ -433,9 +415,6 @@ bool trace_warp_inst_t::parse_from_string(std::string trace){
 			set_addr(i, mem_addresses[i]);
 	}
 
-	// barrier_type bar_type;
-	// reduction_type red_type;
-
 
 	//fill memory space
 	switch(m_opcode){
@@ -469,13 +448,6 @@ bool trace_warp_inst_t::parse_from_string(std::string trace){
 		if(m_opcode == OP_ATOM || m_opcode == OP_ATOMG || m_opcode == OP_RED)
 			m_isatomic = true;
 
-		for(unsigned m=0; m<reg_dsts_num; ++m){
-			out[m]=0;
-			arch_reg.src[m]=-1;
-		}
-		reg_dsts_num=0;
-		outcount=0;
-
 		break;
 	case OP_LDS:
 	case OP_STS:
@@ -489,8 +461,11 @@ bool trace_warp_inst_t::parse_from_string(std::string trace){
 		bar_id = 0;
 		bar_count = (unsigned)-1;
 		bar_type = SYNC;
+		//TO DO
 		//if bar_type = RED;
 		//set bar_type
+		// barrier_type bar_type;
+		// reduction_type red_type;
 		break;
 	default:
 		break;
diff --git a/src/trace-driven/trace_driven.h b/src/trace-driven/trace_driven.h
index 2f97958..5e11448 100644
--- a/src/trace-driven/trace_driven.h
+++ b/src/trace-driven/trace_driven.h
@@ -28,9 +28,6 @@ public:
 
 	}
 
-private:
-
-
 };
 
 class trace_warp_inst_t: public warp_inst_t {
@@ -47,14 +44,11 @@ public:
 	}
 
 	bool parse_from_string(std::string trace);
-	unsigned m_opcode;
 
 private:
-
 	void set_latency(unsigned cat);
 	gpgpu_context* m_gpgpu_context;
-
-
+	unsigned m_opcode;
 };
 
 class trace_kernel_info_t: public kernel_info_t {
@@ -105,15 +99,13 @@ public:
 	bool trace_done();
 	address_type get_start_pc();
 	address_type get_pc();
-	unsigned trace_pc;
 
 private:
-
+	unsigned trace_pc;
 
 };
 
 class trace_shader_core_ctx: public shader_core_ctx {
-
 public:
 	trace_shader_core_ctx(class gpgpu_sim *gpu,
             class simt_core_cluster *cluster,
@@ -130,10 +122,10 @@ public:
 	void init_traces( unsigned start_warp, unsigned end_warp, kernel_info_t &kernel );
 	unsigned trace_sim_inc_thread( kernel_info_t &kernel);
 	virtual void func_exec_inst( warp_inst_t &inst );
-	std::vector<trace_shd_warp_t> m_trace_warp;
+	friend class shader_core_ctx;
 
 private:
-
+	std::vector<trace_shd_warp_t> m_trace_warp;
 
 };