- Fixing cache configuration groupings -> Now <cache configs>, <cache policies>, <MSHR>, <Miss queue/FIFO sizing>

- Fixing default configurations to match the new format and additonal parameters
- Fixing Fermi's 48kB cache configuration

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14370]

6 files changed, 37 insertions, 32 deletions

diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config
index e5108f8..a8eac01 100644
--- a/configs/GTX480/gpgpusim.config
+++ b/configs/GTX480/gpgpusim.config
@@ -38,21 +38,22 @@
 -ptx_opcode_initiation_dp 8,16,8,8,130
 
 # In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
-# <nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>
--gpgpu_cache:dl1  32:128:4:L:L:m:A:N:32:8:8
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+-gpgpu_cache:dl1  32:128:4,L:L:m:N,A:32:8,8
 -gpgpu_shmem_size 49152
 
 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1  64:128:6:L:R:m,A:32:8,8
+#-gpgpu_cache:dl1  64:128:6,L:L:m:N,A:32:8,8
 #-gpgpu_shmem_size 16384
 
 # 64 sets, each 256 bytes 8-way for each memory partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 64:256:8:L:B:m:A:W:32:4:4
+-gpgpu_cache:dl2 64:256:8,L:B:m:W,A:32:4,4
 -gpgpu_cache:dl2_texture_only 0 
 
--gpgpu_cache:il1 4:128:4:L:R:f:A:N:2:32:4
--gpgpu_tex_cache:l1 4:128:24:L:R:m:F:N:128:4:128:2
--gpgpu_const_cache:l1 64:64:2:L:R:f:A:N:2:32:4
+-gpgpu_cache:il1 4:128:4,L:R:f:N,A:2:32,4
+-gpgpu_tex_cache:l1 4:128:24,L:R:m:N,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N,A:2:32,4
 
 -gpgpu_num_reg_banks 16
 
diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config
index 7f43511..638f362 100644
--- a/configs/QuadroFX5800/gpgpusim.config
+++ b/configs/QuadroFX5800/gpgpusim.config
@@ -31,10 +31,12 @@
 -ptx_opcode_initiation_dp 8,8,8,8,130
 
 # memory stage behaviour
--gpgpu_cache:il1 4:256:4:L:R:f:A:N:2:32:4
--gpgpu_tex_cache:l1 8:128:5:L:R:m:F:N:128:4:128:2
--gpgpu_const_cache:l1 64:64:2:L:R:f:A:N:2:32:4
--gpgpu_cache:dl2 16:256:8:L:B:m:A:W:16:4:4
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+-gpgpu_cache:il1 4:256:4,L:R:f:N,A:2:32,4
+-gpgpu_tex_cache:l1 8:128:5,L:R:m:N,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N,A:2:32,4
+-gpgpu_cache:dl2 16:256:8,L:B:m:W,A:16:4,4
 -gpgpu_cache:dl2_texture_only 1
 
 -gpgpu_shmem_warp_parts 2
diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config
index 86944b1..f09e391 100644
--- a/configs/TeslaC2050/gpgpusim.config
+++ b/configs/TeslaC2050/gpgpusim.config
@@ -37,22 +37,24 @@
 -ptx_opcode_latency_dp 8,19,8,8,330
 -ptx_opcode_initiation_dp 8,16,8,8,130
 
+
 # In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
-# <nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>
--gpgpu_cache:dl1  32:128:4:L:L:m:A:N:32:8:8
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+-gpgpu_cache:dl1  32:128:4,L:L:m:N,A:32:8,8
 -gpgpu_shmem_size 49152
 
 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1  64:128:6:L:R:m,A:32:8,8
+#-gpgpu_cache:dl1  64:128:6,L:L:m:N,A:32:8,8
 #-gpgpu_shmem_size 16384
 
 # 64 sets, each 256 bytes 8-way for each memory partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 64:256:8:L:B:m:A:W:32:4:4
+-gpgpu_cache:dl2 64:256:8,L:B:m:W,A:32:4,4
 -gpgpu_cache:dl2_texture_only 0 
 
--gpgpu_cache:il1 4:128:4:L:R:f:A:N:2:32:4
--gpgpu_tex_cache:l1 4:128:24:L:R:m:F:N:128:4:128:2
--gpgpu_const_cache:l1 64:64:2:L:R:f:A:N:2:32:4
+-gpgpu_cache:il1 4:128:4,L:R:f:N,A:2:32,4
+-gpgpu_tex_cache:l1 4:128:24,L:R:m:N,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N,A:2:32,4
 
 -gpgpu_num_reg_banks 16
 
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index bc86b83..fc2d032 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -1,4 +1,4 @@
-// Copyright (c) 2009-2011, Tor M. Aamodt 
+// Copyright (c) 2009-2011, Tor M. Aamodt, Tayler Hetherington
 // The University of British Columbia
 // All rights reserved.
 //
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index bbf62b6..4516e34 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -1,4 +1,4 @@
-// Copyright (c) 2009-2011, Tor M. Aamodt
+// Copyright (c) 2009-2011, Tor M. Aamodt, Tayler Hetherington
 // The University of British Columbia
 // All rights reserved.
 //
@@ -131,9 +131,9 @@ public:
         assert( m_config_string );
         char rp, wp, ap, mshr_type, wap;
 
-        int ntok = sscanf(m_config_string,"%u:%u:%u:%c:%c:%c:%c:%c:%u:%u:%u:%u",
-                          &m_nset, &m_line_sz, &m_assoc, &rp, &wp, &ap,
-                          &mshr_type, &wap, &m_mshr_entries,&m_mshr_max_merge,
+        int ntok = sscanf(m_config_string,"%u:%u:%u,%c:%c:%c:%c,%c:%u:%u,%u:%u",
+                          &m_nset, &m_line_sz, &m_assoc, &rp, &wp, &ap, &wap,
+                          &mshr_type, &m_mshr_entries,&m_mshr_max_merge,
                           &m_miss_queue_size,&m_result_fifo_entries);
 
         if ( ntok < 10 ) {
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 6d9fa87..9c8d327 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -99,8 +99,8 @@ void memory_config::reg_options(class OptionParser * opp)
                            "0");
     option_parser_register(opp, "-gpgpu_cache:dl2", OPT_CSTR, &m_L2_config.m_config_string, 
                    "unified banked L2 data cache config "
-                   " {<nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>}",
-                   "64:128:8:L:R:m,A:16:4,4");
+                   " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}",
+                   "64:128:8,L:B:m:N,A:16:4,4");
     option_parser_register(opp, "-gpgpu_cache:dl2_texture_only", OPT_BOOL, &m_L2_texure_only, 
                            "L2 cache used for texture only",
                            "1");
@@ -147,19 +147,19 @@ void shader_core_config::reg_options(class OptionParser * opp)
                    "1024:32");
     option_parser_register(opp, "-gpgpu_tex_cache:l1", OPT_CSTR, &m_L1T_config.m_config_string, 
                    "per-shader L1 texture cache  (READ-ONLY) config "
-                   " {<nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>:<rf>}",
-                   "8:128:5:L:R:m,F:128:4,128:2");
+                   " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>}",
+                   "8:128:5,L:R:m:N,F:128:4,128:2");
     option_parser_register(opp, "-gpgpu_const_cache:l1", OPT_CSTR, &m_L1C_config.m_config_string, 
                    "per-shader L1 constant memory cache  (READ-ONLY) config "
-                   " {<nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>}",
-                   "64:64:2:L:R:f,A:2:32,4" );
+                   " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} ",
+                   "64:64:2,L:R:f:N,A:2:32,4" );
     option_parser_register(opp, "-gpgpu_cache:il1", OPT_CSTR, &m_L1I_config.m_config_string, 
                    "shader L1 instruction cache config "
-                   " {<nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>}",
-                   "4:256:4:L:R:f,A:2:32,4" );
+                   " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} ",
+                   "4:256:4,L:R:f:N,A:2:32,4" );
     option_parser_register(opp, "-gpgpu_cache:dl1", OPT_CSTR, &m_L1D_config.m_config_string, 
                    "per-shader L1 data cache config "
-                   " {<nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>|none}",
+                   " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}",
                    "none" );
     option_parser_register(opp, "-gpgpu_perfect_mem", OPT_BOOL, &gpgpu_perfect_mem, 
                  "enable perfect memory mode (no cache miss)",